top.srr

synplify环境下 实现 全加器 功能

$ Start of Compile
#Mon Feb 02 09:42:55 2004

Synplicity VHDL Compiler, version Compilers 7.3, Build 041R, built Jul 25 2003
Copyright (C) 1994-2002, Synplicity Inc.  All Rights Reserved

@N:"D:\YHQProj\ModelSim\5-2-2\top.vhd":4:7:4:16|Top entity is set to full_adder.
VHDL syntax check successful!
Synthesizing work.full_adder.behavioral
Post processing for work.full_adder.behavioral
@END
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
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Synplicity Xilinx Technology Mapper, version 7.3, Build 192R, built Jul 25 2003
Copyright (C) 1994-2003, Synplicity Inc.  All Rights Reserved


Net buffering Report for view:work.full_adder(behavioral):
No nets needed buffering.

@N|The option to pack flops in the IOB has not been specified 
Writing Analyst data base D:\YHQProj\Synplify\rev_1\top.srm
Writing EDIF Netlist and constraint files


##### START OF TIMING REPORT #####[
# Timing Report written on Mon Feb 02 09:43:02 2004
#


Top view:               full_adder
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N| This timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N| Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary 
*******************


Worst slack in design: NA






Interface Information 
*********************

		No IO constraint found 


##### END OF TIMING REPORT #####]


---------------------------------------
Resource Usage Report for full_adder 

Mapping to part: xc2s50eft256-7
I/O primitives:
IBUF           3 uses
OBUF           2 uses

I/O Register bits:                  0
Register bits not including I/Os:   0 (0%)

Mapping Summary:
Total  LUTs: 2 (0%)

Mapper successful!
Process took 0h:0m:5s realtime, 0h:0m:5s cputime
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