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MODELSIM 环境下的Verilog 源代码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_adder is				--????
    Port ( a,b,cin: in bit;	--?????????
           s,cout: out bit);	--?????????
end full_adder;
architecture Behavioral of full_adder is	--??????
begin
	process(a,b,cin)			--??????????????????????
		variable ai,bi,ci,si:integer;			--??????
		begin
			if a='0' then ai:=0;		--?bit??????????????????
		else ai:=1;
			end if;
			if b='0'	then bi:=0;
				else bi:=1;
			end if;
			if cin='0' then ci:=0;
				else ci:=1;
			end if;
			si:=ai+bi+ci;	--????????		
			case si is		--?????????????
			when 0=>s<='0';cout<='0';
			when 1=>s<='1';cout<='0';
			when 2=>s<='0';cout<='1';
			when others=>s<='1';cout<='1';
			end case;
	end process;
end Behavioral;