fulladder.cr.mti

MODELSIM 环境下的Verilog 源代码

D:/YHQProj/ModelSim/5-2-2/top.vhd {1 {vcom -work work -87 -explicit D:/YHQProj/ModelSim/5-2-2/top.vhd
Model Technology ModelSim SE vcom 5.7d Compiler 2003.05 May 10 2003
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Compiling entity full_adder
-- Compiling architecture behavioral of full_adder

} {} {}}