_info

MODELSIM 环境下的Verilog 源代码

m255
cModel Technology
dC:\Modeltech_xe\examples
Efull_adder
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
w1075682700
dD:\YHQProj\ModelSim\5-2-2
FD:/YHQProj/ModelSim/5-2-2/top.vhd
l0
L4
V^8]neYP0DgGQkaaceA9?j2
OE;C;5.7d;15
o-work work -87 -explicit
tExplicit T
Abehavioral
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work full_adder ^8]neYP0DgGQkaaceA9?j2
l9
L8
V0NkIEf_;^7Rc0404H9NDQ3
OE;C;5.7d;15
M3 ieee std_logic_1164
M2 ieee std_logic_unsigned
M1 ieee std_logic_arith
o-work work -87 -explicit
tExplicit T