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📄 full_1c20.ptf.4.01

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            OS_MAX_TASKS = "16";
            OS_SCHED_LOCK_EN = "1";
            OS_TASK_IDLE_STK_SIZE = "512";
            OS_TASK_STAT_EN = "1";
            OS_TASK_STAT_STK_SIZE = "512";
            OS_TASK_STAT_STK_CHK_EN = "1";
            OS_TICK_STEP_EN = "1";
            OS_TICKS_PER_SEC = "200";
            OS_FLAG_EN = "1";
            OS_FLAG_WAIT_CLR_EN = "1";
            OS_FLAG_ACCEPT_EN = "1";
            OS_FLAG_DEL_EN = "1";
            OS_FLAG_NAME_SIZE = "32";
            OS_FLAG_QUERY_EN = "1";
            OS_MBOX_EN = "1";
            OS_MBOX_ACCEPT_EN = "1";
            OS_MBOX_DEL_EN = "1";
            OS_MBOX_POST_EN = "1";
            OS_MBOX_POST_OPT_EN = "1";
            OS_MBOX_QUERY_EN = "1";
            OS_MEM_EN = "1";
            OS_MEM_QUERY_EN = "1";
            OS_MEM_NAME_SIZE = "32";
            OS_MUTEX_EN = "1";
            OS_MUTEX_ACCEPT_EN = "1";
            OS_MUTEX_DEL_EN = "1";
            OS_MUTEX_QUERY_EN = "1";
            OS_Q_EN = "1";
            OS_Q_ACCEPT_EN = "1";
            OS_Q_DEL_EN = "1";
            OS_Q_FLUSH_EN = "1";
            OS_Q_POST_EN = "1";
            OS_Q_POST_FRONT_EN = "1";
            OS_Q_POST_OPT_EN = "1";
            OS_Q_QUERY_EN = "1";
            OS_SEM_EN = "1";
            OS_SEM_ACCEPT_EN = "1";
            OS_SEM_DEL_EN = "1";
            OS_SEM_QUERY_EN = "1";
            OS_TASK_CHANGE_PRIO_EN = "1";
            OS_TASK_CREATE_EN = "1";
            OS_TASK_CREATE_EXT_EN = "1";
            OS_TASK_DEL_EN = "1";
            OS_TASK_NAME_SIZE = "32";
            OS_TASK_PROFILE_EN = "1";
            OS_TASK_QUERY_EN = "1";
            OS_TASK_SUSPEND_EN = "1";
            OS_TASK_SW_HOOK_EN = "1";
            OS_TIME_DLY_HMSM_EN = "1";
            OS_TIME_DLY_RESUME_EN = "1";
            OS_TIME_GET_SET_EN = "1";
            OS_TIME_TICK_HOOK_EN = "1";
            LLC_802 = "1";
            MEM_SIZE = "64";
            MEMP_NUM_PBUF = "64";
            MEMP_NUM_UDP_PCB = "2";
            MEMP_NUM_TCP_PCB = "16";
            MEMP_NUM_TCP_PCB_LISTEN = "16";
            MEMP_NUM_TCP_SEG = "64";
            MEMP_NUM_SYS_TIMEOUT = "8";
            MEMP_NUM_NETBUF = "16";
            MEMP_NUM_NETCONN = "16";
            MEMP_NUM_API_MSG = "64";
            MEMP_NUM_TCPIP_MSG = "64";
            MEM_RECLAIM = "1";
            MEMP_RECLAIM = "1";
            PBUF_POOL_SIZE = "64";
            PBUF_POOL_BUFSIZE = "1024";
            LWIP_TCP = "1";
            TCP_TTL = "255";
            TCP_QUEUE_OOSEQ = "1";
            TCP_MSS = "1024";
            TCP_SND_BUF = "1024";
            TCP_SND_QUEUELEN = "65";
            TCP_WND = "1024";
            TCP_MAXRTX = "12";
            TCP_SYNMAXRTX = "4";
            ARP_TABLE_SIZE = "16";
            IP_FORWARD = "0";
            IP_OPTIONS = "1";
            ICMP_TTL = "255";
            LWIP_UDP = "1";
            UDP_TTL = "255";
            STATS = "0";
            LINK_STATS = "1";
            IP_STATS = "1";
            ICMP_STATS = "1";
            UDP_STATS = "1";
            TCP_STATS = "1";
            MEM_STATS = "1";
            MEMP_STATS = "1";
            PBUF_STATS = "1";
            SYS_STATS = "1";
            macaddress = "00-60-80-00-00-00";
            ipaddress = "192.168.128.32";
            netmask = "255.255.255.0";
            gwaddress = "192.168.128.1";
            UART_TX_BUF_SIZE = "256";
            UART_RX_BUF_SIZE = "256";
            UART_XOFF_THRESHOLD_SIZE = "160";
            UART_XON_THRESHOLD_SIZE = "128";
            RS485_TX_BUF_SIZE = "256";
            RS485_RX_BUF_SIZE = "256";
         }
         SYSTEM_BUILDER_INFO 
         {
            Is_Enabled = "0";
         }
      }
      MASTER custom_instruction_master
      {
         PORT_WIRING 
         {
            PORT E_ci_combo_a
            {
               direction = "output";
               type = "combo_a";
               width = "5";
            }
            PORT E_ci_combo_b
            {
               direction = "output";
               type = "combo_b";
               width = "5";
            }
            PORT E_ci_combo_c
            {
               direction = "output";
               type = "combo_c";
               width = "5";
            }
            PORT E_ci_combo_dataa
            {
               direction = "output";
               type = "combo_dataa";
               width = "32";
            }
            PORT E_ci_combo_datab
            {
               direction = "output";
               type = "combo_datab";
               width = "32";
            }
            PORT E_ci_combo_n
            {
               direction = "output";
               type = "combo_n";
               width = "8";
            }
            PORT E_ci_combo_readra
            {
               direction = "output";
               type = "combo_readra";
               width = "1";
            }
            PORT E_ci_combo_readrb
            {
               direction = "output";
               type = "combo_readrb";
               width = "1";
            }
            PORT E_ci_combo_result
            {
               direction = "input";
               type = "combo_result";
               width = "32";
            }
            PORT E_ci_combo_writerc
            {
               direction = "output";
               type = "combo_writerc";
               width = "1";
            }
            PORT clk
            {
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT reset_n
            {
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "nios_custom_instruction";
            Data_Width = "32";
            Address_Width = "8";
            Max_Address_Width = "8";
            Base_Address = "N/A";
            Is_Visible = "0";
            Is_Custom_Instruction = "0";
            Is_Enabled = "1";
         }
      }
   }
   MODULE bswap_cpu
   {
      class = "altera_nios_custom_instr_bitswap";
      class_version = "2.0";
      iss_model_name = "nios2_custom_instruction";
      HDL_INFO 
      {
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/bswap_cpu.vhd";
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_Only_Files = "";
      }
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT dataa
            {
               width = "32";
               direction = "input";
               type = "dataa";
            }
            PORT datab
            {
               width = "32";
               direction = "input";
               type = "datab";
            }
            PORT result
            {
               width = "32";
               direction = "output";
               type = "result";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "nios_custom_instruction";
            Data_Width = "32";
            Address_Width = "0";
            Base_Address = "0x00";
            Is_Custom_Instruction = "1";
            Is_Visible = "0";
            MASTERED_BY cpu/custom_instruction_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/custom_instruction_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Date_Modified = "";
         Is_Enabled = "1";
         Is_Visible = "0";
         Instantiate_In_System_Module = "1";
         Is_Custom_Instruction = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Module_Name = "bitswap_instruction_unit";
         Synthesize_Imported_HDL = "1";
         ci_macro_name = "bit_swap";
         ci_operands = "1";
         ci_cycles = "1";
         ci_has_prefix = "0";
         ci_inst_type = "combinatorial";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE dma
   {
      class = "altera_avalon_dma";
      class_version = "3.2";
      MASTER read_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Max_Address_Width = "32";
            Data_Width = "32";
            Do_Stream_Reads = "1";
            Address_Width = "25";
         }
         PORT_WIRING 
         {
            PORT read_address
            {
               direction = "output";
               type = "address";
               width = "25";
            }
            PORT read_chipselect
            {
               direction = "output";
               type = "chipselect";
               width = "1";
            }
            PORT read_endofpacket
            {
               direction = "input";
               type = "endofpacket";
               width = "1";
            }
            PORT read_flush
            {
               direction = "output";
               type = "flush";
               width = "1";
            }
            PORT read_read_n
            {
               direction = "output";
               type = "read_n";
               width = "1";
            }
            PORT read_readdata
            {
               direction = "input";
               type = "readdata";
               width = "32";
            }
            PORT read_readdatavalid
            {
               direction = "input";
               type = "readdatavalid";
               width = "1";
            }
            PORT read_waitrequest
            {
               direction = "input";
               type = "waitrequest";
               width = "1";
            }
         }
      }
      MASTER write_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Max_Address_Width = "32";
            Data_Width = "32";
            Do_Stream_Writes = "1";
            Address_Width = "25";
         }
         PORT_WIRING 
         {
            PORT write_address
            {
               direction = "output";
               type = "address";
               width = "25";
            }
            PORT write_byteenable
            {
               direction = "output";
               type = "byteenable";
               width = "4";
            }
            PORT write_chipselect
            {
               direction = "output";
               type = "chipselect";
               width = "1";
            }
            PORT write_endofpacket
            {
               direction = "input";
               type = "endofpacket";
               width = "1";
            }
            PORT write_waitrequest
            {
               direction = "input";
               type = "waitrequest";
               width = "1";
            }
            PORT write_write_n
            {
               direction = "output";
               type = "write_n";
               width = "1";
            }
            PORT write_writedata
            {
               direction = "output";
               type = "writedata";
               width = "32";
            }
         }
      }
      SLAVE control_port_slave
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Address_Width = "3";
            Data_Width = "25";
            Has_IRQ = "1";
            Address_Alignment = "native";
            Read_Wait_States = "1";
            Write_Wait_States = "1";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "7";
            }
            Base_Address = "0x009208C0";
         }
         PORT_WIRING 
         {
            PORT clk
            {
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT dma_ctl_address
            {
               direction = "input";
               type = "address";
               width = "3";
            }
            PORT dma_ctl_chipselect
            {
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT dma_ctl_irq
            {
               direction = "output";
               type = "irq";
               width = "1";
            }
            PORT dma_ctl_readdata
            {
               direction = "output";
               type = "readdata";

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