dma.vhd

一个毕业设计

  -- control register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      control <= std_logic_vector'("000010000100");
    elsif clk'event and clk = '1' then
      if std_logic'(clk_en) = '1' then 
        control <= p1_control;
      end if;
    end if;

  end process;

  p1_control <= A_EXT (A_WE_StdLogicVector((std_logic'((((dma_ctl_chipselect AND NOT dma_ctl_write_n) AND to_std_logic((((((std_logic_vector'("00000000000000000000000000000") & (dma_ctl_address)) = std_logic_vector'("00000000000000000000000000000110"))) OR (((std_logic_vector'("00000000000000000000000000000") & (dma_ctl_address)) = std_logic_vector'("00000000000000000000000000000111"))))))))) = '1'), dma_ctl_writedata, (std_logic_vector'("0000000000000") & (control))), 12);
  -- write master length
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      writelength <= std_logic_vector'("0000000000000");
    elsif clk'event and clk = '1' then
      if std_logic'(clk_en) = '1' then 
        writelength <= p1_writelength;
      end if;
    end if;

  end process;

  p1_writelength <= A_EXT (A_WE_StdLogicVector((std_logic'((((dma_ctl_chipselect AND NOT dma_ctl_write_n) AND to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (dma_ctl_address)) = std_logic_vector'("00000000000000000000000000000011"))))))) = '1'), dma_ctl_writedata, (std_logic_vector'("00000000000") & (A_WE_StdLogicVector((std_logic'(((inc_write AND (NOT(writelength_eq_0))))) = '1'), ((std_logic_vector'("0") & (writelength)) - (std_logic_vector'("000000000") & (Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(word) & A_ToStdLogicVector(hw) & A_ToStdLogicVector(byte))))), (std_logic_vector'("0") & (writelength)))))), 13);
  p1_writelength_eq_0 <= (inc_write AND (NOT(writelength_eq_0))) AND to_std_logic((((std_logic_vector'("000000000000000000") & ((((std_logic_vector'("0") & (writelength)) - (std_logic_vector'("000000000") & (Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(word) & A_ToStdLogicVector(hw) & A_ToStdLogicVector(byte)))))))) = std_logic_vector'("00000000000000000000000000000000"))));
  p1_length_eq_0 <= (inc_read AND (NOT(length_eq_0))) AND to_std_logic((((std_logic_vector'("000000000000000000") & ((((std_logic_vector'("0") & (length)) - (std_logic_vector'("000000000") & (Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(word) & A_ToStdLogicVector(hw) & A_ToStdLogicVector(byte)))))))) = std_logic_vector'("00000000000000000000000000000000"))));
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      length_eq_0 <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if std_logic'(clk_en) = '1' then 
        if std_logic'(((dma_ctl_chipselect AND NOT dma_ctl_write_n) AND to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (dma_ctl_address)) = std_logic_vector'("00000000000000000000000000000011")))))) = '1' then 
          length_eq_0 <= std_logic'('0');
        elsif std_logic'(p1_length_eq_0) = '1' then 
          length_eq_0 <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
        end if;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      writelength_eq_0 <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if std_logic'(clk_en) = '1' then 
        if std_logic'(((dma_ctl_chipselect AND NOT dma_ctl_write_n) AND to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (dma_ctl_address)) = std_logic_vector'("00000000000000000000000000000011")))))) = '1' then 
          writelength_eq_0 <= std_logic'('0');
        elsif std_logic'(p1_writelength_eq_0) = '1' then 
          writelength_eq_0 <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
        end if;
      end if;
    end if;

  end process;

  writeaddress_inc <= A_EXT (A_WE_StdLogicVector((std_logic'((wcon)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("000000000000000000000000000") & (Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(word) & A_ToStdLogicVector(hw) & A_ToStdLogicVector(byte))))), 5);
  readaddress_inc <= A_EXT (A_WE_StdLogicVector((std_logic'((rcon)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("000000000000000000000000000") & (Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(word) & A_ToStdLogicVector(hw) & A_ToStdLogicVector(byte))))), 5);
  p1_dma_ctl_readdata <= (((((A_REP(to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (dma_ctl_address)) = std_logic_vector'("00000000000000000000000000000000")))), 25) AND (std_logic_vector'("00000000000000000000") & (status)))) OR ((A_REP(to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (dma_ctl_address)) = std_logic_vector'("00000000000000000000000000000001")))), 25) AND readaddress))) OR ((A_REP(to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (dma_ctl_address)) = std_logic_vector'("00000000000000000000000000000010")))), 25) AND writeaddress))) OR ((A_REP(to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (dma_ctl_address)) = std_logic_vector'("00000000000000000000000000000011")))), 25) AND (std_logic_vector'("000000000000") & (writelength))))) OR ((A_REP(to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (dma_ctl_address)) = std_logic_vector'("00000000000000000000000000000110")))), 25) AND (std_logic_vector'("0000000000000") & (control))));
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      dma_ctl_readdata <= std_logic_vector'("0000000000000000000000000");
    elsif clk'event and clk = '1' then
      if std_logic'(clk_en) = '1' then 
        dma_ctl_readdata <= p1_dma_ctl_readdata;
      end if;
    end if;

  end process;

  done_transaction <= go AND done_write;
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      done <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(clk_en) = '1' then 
        if std_logic'(status_register_write) = '1' then 
          done <= std_logic'('0');
        elsif std_logic'((done_transaction AND NOT d1_done_transaction)) = '1' then 
          done <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
        end if;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_done_transaction <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(clk_en) = '1' then 
        d1_done_transaction <= done_transaction;
      end if;
    end if;

  end process;

  busy <= go AND NOT done_write;
  status(0) <= done;
  status(1) <= busy;
  status(2) <= reop;
  status(3) <= weop;
  status(4) <= len;
  byte <= control(0);
  hw <= control(1);
  word <= control(2);
  go <= control(3);
  i_en <= control(4);
  reen <= control(5);
  ween <= control(6);
  leen <= control(7);
  rcon <= control(8);
  wcon <= control(9);
  doubleword <= control(10);
  quadword <= control(11);
  dma_ctl_irq <= i_en AND done;
  p1_read_got_endofpacket <= NOT status_register_write AND ((read_got_endofpacket OR ((read_endofpacket AND reen))));
  p1_write_got_endofpacket <= NOT status_register_write AND ((write_got_endofpacket OR (((inc_write AND write_endofpacket) AND ween))));
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      read_got_endofpacket <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(clk_en) = '1' then 
        read_got_endofpacket <= p1_read_got_endofpacket;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      write_got_endofpacket <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(clk_en) = '1' then 
        write_got_endofpacket <= p1_write_got_endofpacket;
      end if;
    end if;

  end process;

  flush_fifo <= NOT d1_done_transaction AND done_transaction;
  the_dma_fifo_module : dma_fifo_module
    port map(
      fifo_datavalid => fifo_datavalid,
      fifo_empty => fifo_empty,
      fifo_rd_data => fifo_rd_data,
      p1_fifo_full => p1_fifo_full,
      clk => clk,
      clk_en => clk_en,
      fifo_read => fifo_read,
      fifo_wr_data => fifo_wr_data,
      fifo_write => fifo_write,
      flush_fifo => flush_fifo,
      inc_pending_data => inc_read,
      reset_n => reset_n
    );


  the_dma_mem_read : dma_mem_read
    port map(
      inc_read => inc_read,
      mem_read_n => mem_read_n,
      read_select => read_select,
      clk => clk,
      clk_en => clk_en,
      go => go,
      p1_done_read => p1_done_read,
      p1_fifo_full => p1_fifo_full,
      read_waitrequest => read_waitrequest,
      reset_n => reset_n
    );


  fifo_write <= fifo_write_data_valid;
  the_dma_mem_write : dma_mem_write
    port map(
      fifo_read => fifo_read,
      inc_write => inc_write,
      mem_write_n => mem_write_n,
      write_select => write_select,
      fifo_datavalid => fifo_datavalid,
      write_waitrequest => write_waitrequest
    );


  p1_done_read <= (((leen AND ((p1_length_eq_0 OR (length_eq_0))))) OR p1_read_got_endofpacket) OR p1_done_write;
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      len <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(clk_en) = '1' then 
        if std_logic'(status_register_write) = '1' then 
          len <= std_logic'('0');
        elsif std_logic'(((NOT d1_done_transaction AND done_transaction) AND (writelength_eq_0))) = '1' then 
          len <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
        end if;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      reop <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(clk_en) = '1' then 
        if std_logic'(status_register_write) = '1' then 
          reop <= std_logic'('0');
        elsif std_logic'(((fifo_empty AND read_got_endofpacket) AND d1_read_got_endofpacket)) = '1' then 
          reop <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
        end if;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      weop <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(clk_en) = '1' then 
        if std_logic'(status_register_write) = '1' then 
          weop <= std_logic'('0');
        elsif std_logic'(write_got_endofpacket) = '1' then 
          weop <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
        end if;
      end if;
    end if;

  end process;

  p1_done_write <= (((leen AND ((p1_writelength_eq_0 OR writelength_eq_0)))) OR p1_write_got_endofpacket) OR (fifo_empty AND d1_read_got_endofpacket);
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_read_got_endofpacket <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(clk_en) = '1' then 
        d1_read_got_endofpacket <= read_got_endofpacket;
      end if;
    end if;

  end process;

  -- Write has completed when the length goes to 0, or
  --the write source said end-of-packet, or
  --the read source said end-of-packet and the fifo has emptied.
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      done_write <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(clk_en) = '1' then 
        done_write <= p1_done_write;
      end if;
    end if;

  end process;

  read_address <= readaddress;
  internal_write_address <= writeaddress;
  write_chipselect <= write_select;
  read_chipselect <= read_select;
  read_read_n <= mem_read_n;
  write_write_n <= mem_write_n;
  read_flush <= flush_fifo;
  fifo_rd_data_as_byte <= Std_Logic_Vector'(fifo_rd_data(7 DOWNTO 0) & fifo_rd_data(7 DOWNTO 0) & fifo_rd_data(7 DOWNTO 0) & fifo_rd_data(7 DOWNTO 0));
  fifo_rd_data_as_hw <= Std_Logic_Vector'(fifo_rd_data(15 DOWNTO 0) & fifo_rd_data(15 DOWNTO 0));
  fifo_rd_data_as_word <= fifo_rd_data(31 DOWNTO 0);
  write_writedata <= (((A_REP(byte, 32) AND fifo_rd_data_as_byte)) OR ((A_REP(hw, 32) AND fifo_rd_data_as_hw))) OR ((A_REP(word, 32) AND fifo_rd_data_as_word));
  fifo_write_data_valid <= read_readdatavalid;
  --vhdl renameroo for output signals
  write_address <= internal_write_address;
  --vhdl renameroo for output signals
  write_byteenable <= internal_write_byteenable;

end europa;