dma.vhd

一个毕业设计

  internal_write_select <= fifo_datavalid;
  mem_write_n <= NOT internal_write_select;
  internal_fifo_read <= internal_write_select AND NOT write_waitrequest;
  inc_write <= internal_fifo_read;
  --vhdl renameroo for output signals
  fifo_read <= internal_fifo_read;
  --vhdl renameroo for output signals
  write_select <= internal_write_select;

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- DMA peripheral dma
--Mastered by:
--cpu/data_master; 
--Read slaves:
--sdram/s1; lan91c111/s1; ext_flash/s1; ext_ram/s1; 
--Write slaves:
--sdram/s1; lan91c111/s1; ext_flash/s1; ext_ram/s1; 


entity dma is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal dma_ctl_address : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
                 signal dma_ctl_chipselect : IN STD_LOGIC;
                 signal dma_ctl_write_n : IN STD_LOGIC;
                 signal dma_ctl_writedata : IN STD_LOGIC_VECTOR (24 DOWNTO 0);
                 signal read_endofpacket : IN STD_LOGIC;
                 signal read_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal read_readdatavalid : IN STD_LOGIC;
                 signal read_waitrequest : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal write_endofpacket : IN STD_LOGIC;
                 signal write_waitrequest : IN STD_LOGIC;

              -- outputs:
                 signal dma_ctl_irq : OUT STD_LOGIC;
                 signal dma_ctl_readdata : OUT STD_LOGIC_VECTOR (24 DOWNTO 0);
                 signal dma_ctl_readyfordata : OUT STD_LOGIC;
                 signal read_address : OUT STD_LOGIC_VECTOR (24 DOWNTO 0);
                 signal read_chipselect : OUT STD_LOGIC;
                 signal read_flush : OUT STD_LOGIC;
                 signal read_read_n : OUT STD_LOGIC;
                 signal write_address : OUT STD_LOGIC_VECTOR (24 DOWNTO 0);
                 signal write_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal write_chipselect : OUT STD_LOGIC;
                 signal write_write_n : OUT STD_LOGIC;
                 signal write_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
              );
end entity dma;


architecture europa of dma is
component dma_read_data_mux is 
           port (
                 -- inputs:
                    signal byte : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal clk_en : IN STD_LOGIC;
                    signal dma_ctl_address : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
                    signal dma_ctl_chipselect : IN STD_LOGIC;
                    signal dma_ctl_write_n : IN STD_LOGIC;
                    signal dma_ctl_writedata : IN STD_LOGIC_VECTOR (24 DOWNTO 0);
                    signal hw : IN STD_LOGIC;
                    signal read_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal read_readdatavalid : IN STD_LOGIC;
                    signal readaddress : IN STD_LOGIC_VECTOR (24 DOWNTO 0);
                    signal readaddress_inc : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
                    signal reset_n : IN STD_LOGIC;
                    signal word : IN STD_LOGIC;

                 -- outputs:
                    signal fifo_wr_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
                 );
end component dma_read_data_mux;

component dma_byteenables is 
           port (
                 -- inputs:
                    signal byte : IN STD_LOGIC;
                    signal hw : IN STD_LOGIC;
                    signal word : IN STD_LOGIC;
                    signal write_address : IN STD_LOGIC_VECTOR (24 DOWNTO 0);

                 -- outputs:
                    signal write_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
                 );
end component dma_byteenables;

component dma_fifo_module is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal clk_en : IN STD_LOGIC;
                    signal fifo_read : IN STD_LOGIC;
                    signal fifo_wr_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal fifo_write : IN STD_LOGIC;
                    signal flush_fifo : IN STD_LOGIC;
                    signal inc_pending_data : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal fifo_datavalid : OUT STD_LOGIC;
                    signal fifo_empty : OUT STD_LOGIC;
                    signal fifo_rd_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal p1_fifo_full : OUT STD_LOGIC
                 );
end component dma_fifo_module;

component dma_mem_read is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal clk_en : IN STD_LOGIC;
                    signal go : IN STD_LOGIC;
                    signal p1_done_read : IN STD_LOGIC;
                    signal p1_fifo_full : IN STD_LOGIC;
                    signal read_waitrequest : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal inc_read : OUT STD_LOGIC;
                    signal mem_read_n : OUT STD_LOGIC;
                    signal read_select : OUT STD_LOGIC
                 );
end component dma_mem_read;

component dma_mem_write is 
           port (
                 -- inputs:
                    signal fifo_datavalid : IN STD_LOGIC;
                    signal write_waitrequest : IN STD_LOGIC;

                 -- outputs:
                    signal fifo_read : OUT STD_LOGIC;
                    signal inc_write : OUT STD_LOGIC;
                    signal mem_write_n : OUT STD_LOGIC;
                    signal write_select : OUT STD_LOGIC
                 );
end component dma_mem_write;

                signal busy :  STD_LOGIC;
                signal byte :  STD_LOGIC;
                signal clk_en :  STD_LOGIC;
                signal control :  STD_LOGIC_VECTOR (11 DOWNTO 0);
                signal d1_done_transaction :  STD_LOGIC;
                signal d1_read_got_endofpacket :  STD_LOGIC;
                signal done :  STD_LOGIC;
                signal done_transaction :  STD_LOGIC;
                signal done_write :  STD_LOGIC;
                signal doubleword :  STD_LOGIC;
                signal fifo_datavalid :  STD_LOGIC;
                signal fifo_empty :  STD_LOGIC;
                signal fifo_rd_data :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal fifo_rd_data_as_byte :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal fifo_rd_data_as_hw :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal fifo_rd_data_as_word :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal fifo_read :  STD_LOGIC;
                signal fifo_wr_data :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal fifo_write :  STD_LOGIC;
                signal fifo_write_data_valid :  STD_LOGIC;
                signal flush_fifo :  STD_LOGIC;
                signal go :  STD_LOGIC;
                signal hw :  STD_LOGIC;
                signal i_en :  STD_LOGIC;
                signal inc_read :  STD_LOGIC;
                signal inc_write :  STD_LOGIC;
                signal internal_write_address :  STD_LOGIC_VECTOR (24 DOWNTO 0);
                signal internal_write_byteenable :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal leen :  STD_LOGIC;
                signal len :  STD_LOGIC;
                signal length :  STD_LOGIC_VECTOR (12 DOWNTO 0);
                signal length_eq_0 :  STD_LOGIC;
                signal mem_read_n :  STD_LOGIC;
                signal mem_write_n :  STD_LOGIC;
                signal p1_control :  STD_LOGIC_VECTOR (11 DOWNTO 0);
                signal p1_dma_ctl_readdata :  STD_LOGIC_VECTOR (24 DOWNTO 0);
                signal p1_done_read :  STD_LOGIC;
                signal p1_done_write :  STD_LOGIC;
                signal p1_fifo_full :  STD_LOGIC;
                signal p1_length :  STD_LOGIC_VECTOR (12 DOWNTO 0);
                signal p1_length_eq_0 :  STD_LOGIC;
                signal p1_read_got_endofpacket :  STD_LOGIC;
                signal p1_readaddress :  STD_LOGIC_VECTOR (24 DOWNTO 0);
                signal p1_write_got_endofpacket :  STD_LOGIC;
                signal p1_writeaddress :  STD_LOGIC_VECTOR (24 DOWNTO 0);
                signal p1_writelength :  STD_LOGIC_VECTOR (12 DOWNTO 0);
                signal p1_writelength_eq_0 :  STD_LOGIC;
                signal quadword :  STD_LOGIC;
                signal rcon :  STD_LOGIC;
                signal read_got_endofpacket :  STD_LOGIC;
                signal read_select :  STD_LOGIC;
                signal readaddress :  STD_LOGIC_VECTOR (24 DOWNTO 0);
                signal readaddress_inc :  STD_LOGIC_VECTOR (4 DOWNTO 0);
                signal reen :  STD_LOGIC;
                signal reop :  STD_LOGIC;
                signal status :  STD_LOGIC_VECTOR (4 DOWNTO 0);
                signal status_register_write :  STD_LOGIC;
                signal wcon :  STD_LOGIC;
                signal ween :  STD_LOGIC;
                signal weop :  STD_LOGIC;
                signal word :  STD_LOGIC;
                signal write_got_endofpacket :  STD_LOGIC;
                signal write_select :  STD_LOGIC;
                signal writeaddress :  STD_LOGIC_VECTOR (24 DOWNTO 0);
                signal writeaddress_inc :  STD_LOGIC_VECTOR (4 DOWNTO 0);
                signal writelength :  STD_LOGIC_VECTOR (12 DOWNTO 0);
                signal writelength_eq_0 :  STD_LOGIC;

begin

  clk_en <= std_logic'('1');
  the_dma_read_data_mux : dma_read_data_mux
    port map(
      fifo_wr_data => fifo_wr_data,
      byte => byte,
      clk => clk,
      clk_en => clk_en,
      dma_ctl_address => dma_ctl_address,
      dma_ctl_chipselect => dma_ctl_chipselect,
      dma_ctl_write_n => dma_ctl_write_n,
      dma_ctl_writedata => dma_ctl_writedata,
      hw => hw,
      read_readdata => read_readdata,
      read_readdatavalid => read_readdatavalid,
      readaddress => readaddress,
      readaddress_inc => readaddress_inc,
      reset_n => reset_n,
      word => word
    );


  the_dma_byteenables : dma_byteenables
    port map(
      write_byteenable => internal_write_byteenable,
      byte => byte,
      hw => hw,
      word => word,
      write_address => internal_write_address
    );


  dma_ctl_readyfordata <= NOT busy;
  status_register_write <= (dma_ctl_chipselect AND NOT dma_ctl_write_n) AND to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (dma_ctl_address)) = std_logic_vector'("00000000000000000000000000000000"))));
  -- read address
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      readaddress <= std_logic_vector'("0000000000000000000000000");
    elsif clk'event and clk = '1' then
      if std_logic'(clk_en) = '1' then 
        readaddress <= p1_readaddress;
      end if;
    end if;

  end process;

  p1_readaddress <= A_EXT (A_WE_StdLogicVector((std_logic'((((dma_ctl_chipselect AND NOT dma_ctl_write_n) AND to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (dma_ctl_address)) = std_logic_vector'("00000000000000000000000000000001"))))))) = '1'), (std_logic_vector'("0") & (dma_ctl_writedata)), A_WE_StdLogicVector((std_logic'((inc_read)) = '1'), (((std_logic_vector'("0") & (readaddress)) + (std_logic_vector'("000000000000000000000") & (readaddress_inc)))), (std_logic_vector'("0") & (readaddress)))), 25);
  -- write address
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      writeaddress <= std_logic_vector'("0000000000000000000000000");
    elsif clk'event and clk = '1' then
      if std_logic'(clk_en) = '1' then 
        writeaddress <= p1_writeaddress;
      end if;
    end if;

  end process;

  p1_writeaddress <= A_EXT (A_WE_StdLogicVector((std_logic'((((dma_ctl_chipselect AND NOT dma_ctl_write_n) AND to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (dma_ctl_address)) = std_logic_vector'("00000000000000000000000000000010"))))))) = '1'), (std_logic_vector'("0") & (dma_ctl_writedata)), A_WE_StdLogicVector((std_logic'((inc_write)) = '1'), (((std_logic_vector'("0") & (writeaddress)) + (std_logic_vector'("000000000000000000000") & (writeaddress_inc)))), (std_logic_vector'("0") & (writeaddress)))), 25);
  -- length in bytes
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      length <= std_logic_vector'("0000000000000");
    elsif clk'event and clk = '1' then
      if std_logic'(clk_en) = '1' then 
        length <= p1_length;
      end if;
    end if;

  end process;

  p1_length <= A_EXT (A_WE_StdLogicVector((std_logic'((((dma_ctl_chipselect AND NOT dma_ctl_write_n) AND to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (dma_ctl_address)) = std_logic_vector'("00000000000000000000000000000011"))))))) = '1'), dma_ctl_writedata, (std_logic_vector'("00000000000") & (A_WE_StdLogicVector((std_logic'(((inc_read AND (NOT(length_eq_0))))) = '1'), ((std_logic_vector'("0") & (length)) - (std_logic_vector'("000000000") & (Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(word) & A_ToStdLogicVector(hw) & A_ToStdLogicVector(byte))))), (std_logic_vector'("0") & (length)))))), 13);