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signal fifo_read : IN STD_LOGIC;
signal fifo_wr_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_write : IN STD_LOGIC;
signal flush_fifo : IN STD_LOGIC;
signal inc_pending_data : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal fifo_datavalid : OUT STD_LOGIC;
signal fifo_empty : OUT STD_LOGIC;
signal fifo_rd_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal p1_fifo_full : OUT STD_LOGIC
);
end entity dma_fifo_module;
architecture europa of dma_fifo_module is
component dma_fifo_module_fifo_ram_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal rdaddress : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rdclken : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal wraddress : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal wrclock : IN STD_LOGIC;
signal wren : IN STD_LOGIC;
-- outputs:
signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component dma_fifo_module_fifo_ram_module;
signal estimated_rdaddress : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal estimated_wraddress : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal fifo_dec : STD_LOGIC;
signal fifo_full : STD_LOGIC;
signal fifo_inc : STD_LOGIC;
signal fifo_ram_q : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_fifo_empty : STD_LOGIC;
signal internal_p1_fifo_full : STD_LOGIC;
signal last_write_collision : STD_LOGIC;
signal last_write_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal module_input : STD_LOGIC;
signal p1_estimated_wraddress : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal p1_fifo_empty : STD_LOGIC;
signal p1_wraddress : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rdaddress : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rdaddress_reg : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal wraddress : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal write_collision : STD_LOGIC;
begin
p1_wraddress <= A_EXT (A_WE_StdLogicVector((std_logic'((fifo_write)) = '1'), ((std_logic_vector'("000000000000000000000000000000") & (wraddress)) - std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("000000000000000000000000000000") & (wraddress))), 3);
process (clk, reset_n)
begin
if reset_n = '0' then
wraddress <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
if std_logic'(flush_fifo) = '1' then
wraddress <= std_logic_vector'("000");
else
wraddress <= p1_wraddress;
end if;
end if;
end if;
end process;
rdaddress <= A_EXT (A_WE_StdLogicVector((std_logic'(flush_fifo) = '1'), std_logic_vector'("000000000000000000000000000000000"), A_WE_StdLogicVector((std_logic'(fifo_read) = '1'), (((std_logic_vector'("000000000000000000000000000000") & (rdaddress_reg)) - std_logic_vector'("000000000000000000000000000000001"))), (std_logic_vector'("000000000000000000000000000000") & (rdaddress_reg)))), 3);
process (clk, reset_n)
begin
if reset_n = '0' then
rdaddress_reg <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then
rdaddress_reg <= rdaddress;
end if;
end if;
end process;
fifo_datavalid <= NOT internal_fifo_empty;
fifo_inc <= fifo_write AND NOT fifo_read;
fifo_dec <= fifo_read AND NOT fifo_write;
estimated_rdaddress <= A_EXT (((std_logic_vector'("000000000000000000000000000000") & (rdaddress_reg)) - std_logic_vector'("000000000000000000000000000000001")), 3);
p1_estimated_wraddress <= A_EXT (A_WE_StdLogicVector((std_logic'((inc_pending_data)) = '1'), ((std_logic_vector'("000000000000000000000000000000") & (estimated_wraddress)) - std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("000000000000000000000000000000") & (estimated_wraddress))), 3);
process (clk, reset_n)
begin
if reset_n = '0' then
estimated_wraddress <= A_REP(std_logic'('1'), 3);
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
if std_logic'(flush_fifo) = '1' then
estimated_wraddress <= A_REP(std_logic'('1'), 3);
else
estimated_wraddress <= p1_estimated_wraddress;
end if;
end if;
end if;
end process;
p1_fifo_empty <= flush_fifo OR ((((NOT fifo_inc AND internal_fifo_empty)) OR ((fifo_dec AND to_std_logic(((wraddress = estimated_rdaddress)))))));
process (clk, reset_n)
begin
if reset_n = '0' then
internal_fifo_empty <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
internal_fifo_empty <= p1_fifo_empty;
end if;
end if;
end process;
internal_p1_fifo_full <= NOT flush_fifo AND ((((NOT fifo_dec AND fifo_full)) OR ((inc_pending_data AND to_std_logic(((estimated_wraddress = rdaddress)))))));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_full <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
fifo_full <= internal_p1_fifo_full;
end if;
end if;
end process;
write_collision <= fifo_write AND to_std_logic(((wraddress = rdaddress)));
process (clk, reset_n)
begin
if reset_n = '0' then
last_write_data <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(write_collision) = '1' then
last_write_data <= fifo_wr_data;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
last_write_collision <= std_logic'('0');
elsif clk'event and clk = '1' then
if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then
if std_logic'(write_collision) = '1' then
last_write_collision <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
elsif std_logic'(fifo_read) = '1' then
last_write_collision <= std_logic'('0');
end if;
end if;
end if;
end process;
fifo_rd_data <= A_WE_StdLogicVector((std_logic'(last_write_collision) = '1'), last_write_data, fifo_ram_q);
dma_fifo_module_fifo_ram : dma_fifo_module_fifo_ram_module
port map(
q => fifo_ram_q,
clk => clk,
data => fifo_wr_data,
rdaddress => rdaddress,
rdclken => module_input,
reset_n => reset_n,
wraddress => wraddress,
wrclock => clk,
wren => fifo_write
);
module_input <= std_logic'('1');
--vhdl renameroo for output signals
fifo_empty <= internal_fifo_empty;
--vhdl renameroo for output signals
p1_fifo_full <= internal_p1_fifo_full;
end europa;
library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dma_mem_read is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal clk_en : IN STD_LOGIC;
signal go : IN STD_LOGIC;
signal p1_done_read : IN STD_LOGIC;
signal p1_fifo_full : IN STD_LOGIC;
signal read_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal inc_read : OUT STD_LOGIC;
signal mem_read_n : OUT STD_LOGIC;
signal read_select : OUT STD_LOGIC
);
end entity dma_mem_read;
architecture europa of dma_mem_read is
signal dma_mem_read_access : STD_LOGIC;
signal dma_mem_read_idle : STD_LOGIC;
signal internal_read_select : STD_LOGIC;
signal p1_read_select : STD_LOGIC;
begin
mem_read_n <= NOT internal_read_select;
process (clk, reset_n)
begin
if reset_n = '0' then
internal_read_select <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
internal_read_select <= p1_read_select;
end if;
end if;
end process;
inc_read <= internal_read_select AND NOT read_waitrequest;
-- Transitions into state 'idle'.
process (clk, reset_n)
begin
if reset_n = '0' then
dma_mem_read_idle <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
dma_mem_read_idle <= to_std_logic((((((((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dma_mem_read_idle))) = std_logic_vector'("00000000000000000000000000000001"))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(go))) = std_logic_vector'("00000000000000000000000000000000"))))) OR (((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dma_mem_read_idle))) = std_logic_vector'("00000000000000000000000000000001"))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(p1_done_read))) = std_logic_vector'("00000000000000000000000000000001")))))) OR (((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dma_mem_read_idle))) = std_logic_vector'("00000000000000000000000000000001"))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(p1_fifo_full))) = std_logic_vector'("00000000000000000000000000000001")))))) OR ((((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dma_mem_read_access))) = std_logic_vector'("00000000000000000000000000000001"))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(read_waitrequest))) = std_logic_vector'("00000000000000000000000000000000")))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(p1_fifo_full))) = std_logic_vector'("00000000000000000000000000000001")))))) OR ((((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dma_mem_read_access))) = std_logic_vector'("00000000000000000000000000000001"))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(p1_done_read))) = std_logic_vector'("00000000000000000000000000000001")))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(read_waitrequest))) = std_logic_vector'("00000000000000000000000000000000")))))));
end if;
end if;
end process;
-- Transitions into state 'access'.
process (clk, reset_n)
begin
if reset_n = '0' then
dma_mem_read_access <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
dma_mem_read_access <= to_std_logic((((((((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dma_mem_read_idle))) = std_logic_vector'("00000000000000000000000000000001"))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(p1_done_read))) = std_logic_vector'("00000000000000000000000000000000")))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(go))) = std_logic_vector'("00000000000000000000000000000001")))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(p1_fifo_full))) = std_logic_vector'("00000000000000000000000000000000"))))) OR (((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dma_mem_read_access))) = std_logic_vector'("00000000000000000000000000000001"))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(read_waitrequest))) = std_logic_vector'("00000000000000000000000000000001")))))) OR (((((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dma_mem_read_access))) = std_logic_vector'("00000000000000000000000000000001"))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(p1_done_read))) = std_logic_vector'("00000000000000000000000000000000")))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(read_waitrequest))) = std_logic_vector'("00000000000000000000000000000000")))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(p1_fifo_full))) = std_logic_vector'("00000000000000000000000000000000")))))));
end if;
end if;
end process;
p1_read_select <= Vector_To_Std_Logic((((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((dma_mem_read_access AND to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(read_waitrequest))) = std_logic_vector'("00000000000000000000000000000001"))))))))) AND std_logic_vector'("00000000000000000000000000000001"))) OR (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((((dma_mem_read_access AND to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(p1_done_read))) = std_logic_vector'("00000000000000000000000000000000"))))) AND to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(p1_fifo_full))) = std_logic_vector'("00000000000000000000000000000000"))))) AND to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(read_waitrequest))) = std_logic_vector'("00000000000000000000000000000000"))))))))) AND std_logic_vector'("00000000000000000000000000000001")))) OR (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((((dma_mem_read_idle AND to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(go))) = std_logic_vector'("00000000000000000000000000000001"))))) AND to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(p1_done_read))) = std_logic_vector'("00000000000000000000000000000000"))))) AND to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(p1_fifo_full))) = std_logic_vector'("00000000000000000000000000000000"))))))))) AND std_logic_vector'("00000000000000000000000000000001")))));
--vhdl renameroo for output signals
read_select <= internal_read_select;
end europa;
library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dma_mem_write is
port (
-- inputs:
signal fifo_datavalid : IN STD_LOGIC;
signal write_waitrequest : IN STD_LOGIC;
-- outputs:
signal fifo_read : OUT STD_LOGIC;
signal inc_write : OUT STD_LOGIC;
signal mem_write_n : OUT STD_LOGIC;
signal write_select : OUT STD_LOGIC
);
end entity dma_mem_write;
architecture europa of dma_mem_write is
signal internal_fifo_read : STD_LOGIC;
signal internal_write_select : STD_LOGIC;
begin
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