dma.vhd

一个毕业设计

--Copyright (C) 1991-2004 Altera Corporation
--Any megafunction design, and related net list (encrypted or decrypted),
--support information, device programming or simulation file, and any other
--associated documentation or information provided by Altera or a partner
--under Altera's Megafunction Partnership Program may be used only to
--program PLD devices (but not masked PLD devices) from Altera.  Any other
--use of such megafunction design, net list, support information, device
--programming or simulation file, or any other related documentation or
--information is prohibited for any other purpose, including, but not
--limited to modification, reverse engineering, de-compiling, or use with
--any other silicon devices, unless such use is explicitly licensed under
--a separate agreement with Altera or a megafunction partner.  Title to
--the intellectual property, including patents, copyrights, trademarks,
--trade secrets, or maskworks, embodied in any such megafunction design,
--net list, support information, device programming or simulation file, or
--any other related documentation or information provided by Altera or a
--megafunction partner, remains with Altera, the megafunction partner, or
--their respective licensors.  No other licenses, including any licenses
--needed under any third party's intellectual property, are provided herein.
--Copying or modifying any file, or portion thereof, to which this notice
--is attached violates this copyright.

library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity dma_read_data_mux is 
        port (
              -- inputs:
                 signal byte : IN STD_LOGIC;
                 signal clk : IN STD_LOGIC;
                 signal clk_en : IN STD_LOGIC;
                 signal dma_ctl_address : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
                 signal dma_ctl_chipselect : IN STD_LOGIC;
                 signal dma_ctl_write_n : IN STD_LOGIC;
                 signal dma_ctl_writedata : IN STD_LOGIC_VECTOR (24 DOWNTO 0);
                 signal hw : IN STD_LOGIC;
                 signal read_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal read_readdatavalid : IN STD_LOGIC;
                 signal readaddress : IN STD_LOGIC_VECTOR (24 DOWNTO 0);
                 signal readaddress_inc : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
                 signal reset_n : IN STD_LOGIC;
                 signal word : IN STD_LOGIC;

              -- outputs:
                 signal fifo_wr_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
              );
end entity dma_read_data_mux;


architecture europa of dma_read_data_mux is
                signal control_write :  STD_LOGIC;
                signal read_data_mux_input :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal readdata_mux_select :  STD_LOGIC_VECTOR (1 DOWNTO 0);

begin

  control_write <= (dma_ctl_chipselect AND NOT dma_ctl_write_n) AND to_std_logic((((((std_logic_vector'("00000000000000000000000000000") & (dma_ctl_address)) = std_logic_vector'("00000000000000000000000000000110"))) OR (((std_logic_vector'("00000000000000000000000000000") & (dma_ctl_address)) = std_logic_vector'("00000000000000000000000000000111"))))));
  read_data_mux_input <= A_EXT (A_WE_StdLogicVector((std_logic'(((control_write AND (dma_ctl_writedata(3))))) = '1'), (std_logic_vector'("0000") & (readaddress(1 DOWNTO 0))), A_WE_StdLogicVector((std_logic'((read_readdatavalid)) = '1'), (((std_logic_vector'("0000") & (readdata_mux_select)) + (std_logic_vector'("0") & (readaddress_inc)))), (std_logic_vector'("0000") & (readdata_mux_select)))), 2);
  -- Reset value: the transaction size bits of the read address reset value.
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      readdata_mux_select <= std_logic_vector'("00");
    elsif clk'event and clk = '1' then
      if std_logic'(clk_en) = '1' then 
        readdata_mux_select <= read_data_mux_input(1 DOWNTO 0);
      end if;
    end if;

  end process;

  fifo_wr_data(31 DOWNTO 16) <= read_readdata(31 DOWNTO 16);
  fifo_wr_data(15 DOWNTO 8) <= (((A_REP(((hw AND to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(readdata_mux_select(1)))) = std_logic_vector'("00000000000000000000000000000000")))))) , 8) AND read_readdata(15 DOWNTO 8))) OR ((A_REP(((hw AND to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(readdata_mux_select(1)))) = std_logic_vector'("00000000000000000000000000000001")))))) , 8) AND read_readdata(31 DOWNTO 24)))) OR ((A_REP(word, 8) AND read_readdata(15 DOWNTO 8)));
  fifo_wr_data(7 DOWNTO 0) <= (((((((A_REP(((byte AND to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (readdata_mux_select(1 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000000000")))))) , 8) AND read_readdata(7 DOWNTO 0))) OR ((A_REP(((byte AND to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (readdata_mux_select(1 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000000001")))))) , 8) AND read_readdata(15 DOWNTO 8)))) OR ((A_REP(((byte AND to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (readdata_mux_select(1 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000000010")))))) , 8) AND read_readdata(23 DOWNTO 16)))) OR ((A_REP(((byte AND to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (readdata_mux_select(1 DOWNTO 0))) = std_logic_vector'("00000000000000000000000000000011")))))) , 8) AND read_readdata(31 DOWNTO 24)))) OR ((A_REP(((hw AND to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(readdata_mux_select(1)))) = std_logic_vector'("00000000000000000000000000000000")))))) , 8) AND read_readdata(7 DOWNTO 0)))) OR ((A_REP(((hw AND to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(readdata_mux_select(1)))) = std_logic_vector'("00000000000000000000000000000001")))))) , 8) AND read_readdata(23 DOWNTO 16)))) OR ((A_REP(word, 8) AND read_readdata(7 DOWNTO 0)));

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity dma_byteenables is 
        port (
              -- inputs:
                 signal byte : IN STD_LOGIC;
                 signal hw : IN STD_LOGIC;
                 signal word : IN STD_LOGIC;
                 signal write_address : IN STD_LOGIC_VECTOR (24 DOWNTO 0);

              -- outputs:
                 signal write_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
              );
end entity dma_byteenables;


architecture europa of dma_byteenables is
                signal wa_1_is_0 :  STD_LOGIC;
                signal wa_1_is_1 :  STD_LOGIC;
                signal wa_1_to_0_is_0 :  STD_LOGIC;
                signal wa_1_to_0_is_1 :  STD_LOGIC;
                signal wa_1_to_0_is_2 :  STD_LOGIC;
                signal wa_1_to_0_is_3 :  STD_LOGIC;

begin

  wa_1_to_0_is_3 <= to_std_logic((write_address(1 DOWNTO 0) = std_logic_vector'("11")));
  wa_1_to_0_is_2 <= to_std_logic((write_address(1 DOWNTO 0) = std_logic_vector'("10")));
  wa_1_to_0_is_1 <= to_std_logic((write_address(1 DOWNTO 0) = std_logic_vector'("01")));
  wa_1_to_0_is_0 <= to_std_logic((write_address(1 DOWNTO 0) = std_logic_vector'("00")));
  wa_1_is_1 <= to_std_logic((std_logic'(write_address(1)) = std_logic'(std_logic'('1'))));
  wa_1_is_0 <= to_std_logic((std_logic'(write_address(1)) = std_logic'(std_logic'('0'))));
  write_byteenable <= (((A_REP(byte, 4) AND Std_Logic_Vector'(A_ToStdLogicVector(wa_1_to_0_is_3) & A_ToStdLogicVector(wa_1_to_0_is_2) & A_ToStdLogicVector(wa_1_to_0_is_1) & A_ToStdLogicVector(wa_1_to_0_is_0)))) OR ((A_REP(hw, 4) AND Std_Logic_Vector'(A_ToStdLogicVector(wa_1_is_1) & A_ToStdLogicVector(wa_1_is_1) & A_ToStdLogicVector(wa_1_is_0) & A_ToStdLogicVector(wa_1_is_0))))) OR ((A_REP(word, 4) AND std_logic_vector'("1111")));

end europa;


--exemplar translate_off

library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity dma_fifo_module_fifo_ram_module is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal rdaddress : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
                 signal rdclken : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal wraddress : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
                 signal wrclock : IN STD_LOGIC;
                 signal wren : IN STD_LOGIC;

              -- outputs:
                 signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
              );
end entity dma_fifo_module_fifo_ram_module;


architecture europa of dma_fifo_module_fifo_ram_module is
              signal internal_q :  STD_LOGIC_VECTOR (31 DOWNTO 0);
              TYPE mem_array is ARRAY( 7 DOWNTO 0) of STD_LOGIC_VECTOR(31 DOWNTO 0);
              signal read_address :  STD_LOGIC_VECTOR (2 DOWNTO 0);

begin
   process (wrclock, clk) -- MG
    VARIABLE rd_address_internal : STD_LOGIC_VECTOR (2 DOWNTO 0) := (others => '0');
    VARIABLE wr_address_internal : STD_LOGIC_VECTOR (2 DOWNTO 0) := (others => '0');
    variable Marc_Gaucherons_Memory_Variable : mem_array; -- MG
    
    begin
      -- Write data
      if wrclock'event and wrclock = '1' then
        wr_address_internal := wraddress;
        if wren = '1' then 
          Marc_Gaucherons_Memory_Variable(CONV_INTEGER(UNSIGNED(wr_address_internal))) := data;
        end if;
      end if;

      -- read data
      q <= Marc_Gaucherons_Memory_Variable(CONV_INTEGER(UNSIGNED(rd_address_internal)));
      
			 IF clk'event AND clk = '1' AND rdclken = '1' THEN
                            rd_address_internal := rdaddress;
                         END IF;
                        


    end process;
end europa;

--exemplar translate_on


--synthesis read_comments_as_HDL on
--library altera_vhdl_support;
--use altera_vhdl_support.altera_vhdl_support_lib.all;
--
--library ieee;
--use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
--
--entity dma_fifo_module_fifo_ram_module is 
--        port (
--              
--                 signal clk : IN STD_LOGIC;
--                 signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
--                 signal rdaddress : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
--                 signal rdclken : IN STD_LOGIC;
--                 signal reset_n : IN STD_LOGIC;
--                 signal wraddress : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
--                 signal wrclock : IN STD_LOGIC;
--                 signal wren : IN STD_LOGIC;
--
--              
--                 signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
--              );
--end entity dma_fifo_module_fifo_ram_module;
--
--
--architecture europa of dma_fifo_module_fifo_ram_module is
--  component lpm_ram_dp is
--GENERIC (
--      lpm_file : STRING;
--        lpm_hint : STRING;
--        lpm_indata : STRING;
--        lpm_outdata : STRING;
--        lpm_rdaddress_control : STRING;
--        lpm_width : NATURAL;
--        lpm_widthad : NATURAL;
--        lpm_wraddress_control : STRING;
--        suppress_memory_conversion_warnings : STRING
--      );
--    PORT (
--    signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
--        signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
--        signal rdaddress : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
--        signal rdclken : IN STD_LOGIC;
--        signal rdclock : IN STD_LOGIC;
--        signal wraddress : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
--        signal wrclock : IN STD_LOGIC;
--        signal wren : IN STD_LOGIC
--      );
--  end component lpm_ram_dp;
--                signal internal_q :  STD_LOGIC_VECTOR (31 DOWNTO 0);
--                TYPE mem_array is ARRAY( 7 DOWNTO 0) of STD_LOGIC_VECTOR(31 DOWNTO 0);
--                signal read_address :  STD_LOGIC_VECTOR (2 DOWNTO 0);
--
--begin
--
--  process (rdaddress)
--  begin
--      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
--        read_address <= rdaddress;
--      end if;
--
--  end process;
--
--  lpm_ram_dp_component : lpm_ram_dp
--    generic map(
--      lpm_file => "UNUSED",
--      lpm_hint => "USE_EAB=OFF",
--      lpm_indata => "REGISTERED",
--      lpm_outdata => "UNREGISTERED",
--      lpm_rdaddress_control => "REGISTERED",
--      lpm_width => 32,
--      lpm_widthad => 3,
--      lpm_wraddress_control => "REGISTERED",
--      suppress_memory_conversion_warnings => "ON"
--    )
--    port map(
--            data => data,
--            q => internal_q,
--            rdaddress => read_address,
--            rdclken => rdclken,
--            rdclock => clk,
--            wraddress => wraddress,
--            wrclock => wrclock,
--            wren => wren
--    );
--
--  
--  q <= internal_q;
--end europa;
--
--synthesis read_comments_as_HDL off

library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity dma_fifo_module is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal clk_en : IN STD_LOGIC;