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📄 full_featured.tan.rpt

📁 一个毕业设计
💻 RPT
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; Worst-case minimum tpd                                           ; N/A       ; None                              ; 1.879 ns                         ; altera_internal_jtag~TDO                                                                                                                                                 ; altera_reserved_tdo                                                                                                     ;
; Clock Setup: 'connector_pll:inst2|altpll:altpll_component|_clk1' ; 2.325 ns  ; 100.00 MHz ( period = 10.000 ns ) ; N/A                              ; full_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo|lpm_counter:fiforp_rtl_1|alt_counter_stratix:wysi_counter|safe_q[1] ; full_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_pib:the_cpu_nios2_oci_pib|tr_data_reg[8]       ;
; Clock Setup: 'connector_pll:inst2|altpll:altpll_component|_clk0' ; 4.684 ns  ; 50.00 MHz ( period = 20.000 ns )  ; 65.29 MHz ( period = 15.316 ns ) ; full_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|internal_cpu_instruction_master_read_data_valid_sdram_s1_shift_register[3]                                               ; full_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|select_n_to_the_ext_ram~reg0            ;
; Clock Setup: 'PLD_CLOCKINPUT[1]'                                 ; 15.909 ns ; 50.00 MHz ( period = 20.000 ns )  ; 244.44 MHz ( period = 4.091 ns ) ; delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|alt_counter_stratix:wysi_counter|safe_q[1]                                                  ; delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|alt_counter_stratix:wysi_counter|safe_q[3] ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'                      ; N/A       ; None                              ; 89.57 MHz ( period = 11.164 ns ) ; sld_hub:sld_hub_inst|jtag_debug_mode_usr1                                                                                                                                ; full_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate                            ;
+------------------------------------------------------------------+-----------+-----------------------------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                  ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Clock Node Name                                      ; Clock Setting Name ; Type       ; Fmax Requirement ; Based on          ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ;
+------------------------------------------------------+--------------------+------------+------------------+-------------------+-----------------------+---------------------+-----------+
; sdram_pll:inst1|altpll:altpll_component|_extclk0     ;                    ; PLL output ; 50.0 MHz         ; PLD_CLKFB         ; 1                     ; 1                   ; -5.408 ns ;
; connector_pll:inst2|altpll:altpll_component|_clk0    ;                    ; PLL output ; 50.0 MHz         ; PLD_CLOCKINPUT[1] ; 1                     ; 1                   ; -1.875 ns ;
; connector_pll:inst2|altpll:altpll_component|_clk1    ;                    ; PLL output ; 100.0 MHz        ; PLD_CLOCKINPUT[1] ; 2                     ; 1                   ; -1.875 ns ;
; connector_pll:inst2|altpll:altpll_component|_extclk0 ;                    ; PLL output ; 50.0 MHz         ; PLD_CLOCKINPUT[1] ; 1                     ; 1                   ; -1.875 ns ;
; PLD_CLKFB                                            ;                    ; User Pin   ; 50.0 MHz         ; NONE              ; N/A                   ; N/A                 ; N/A       ;
; PLD_CLOCKINPUT[1]                                    ;                    ; User Pin   ; 50.0 MHz         ; NONE              ; N/A                   ; N/A                 ; N/A       ;
; altera_internal_jtag~TCKUTAP                         ;                    ; User Pin   ; NONE             ; NONE              ; N/A                   ; N/A                 ; N/A       ;
; altera_internal_jtag~UPDATEUSER                      ;                    ; User Pin   ; NONE             ; NONE              ; N/A                   ; N/A                 ; N/A       ;
+------------------------------------------------------+--------------------+------------+------------------+-------------------+-----------------------+---------------------+-----------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'connector_pll:inst2|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Slack                                   ; Actual fmax (period)                                       ; From                                                                                                                             ; To                                                                                                               ; From Clock                                        ; To Clock                                          ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+---------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 4.684 ns                                ; 65.29 MHz ( period = 15.316 ns )                           ; full_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|internal_cpu_instruction_master_read_data_valid_sdram_s1_shift_register[3]       ; full_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|select_n_to_the_ext_ram~reg0     ; connector_pll:inst2|altpll:altpll_component|_clk0 ; connector_pll:inst2|altpll:altpll_component|_clk0 ; 20.000 ns                   ; 19.368 ns                 ; 14.684 ns               ;
; 4.785 ns                                ; 65.72 MHz ( period = 15.215 ns )                           ; full_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|internal_d_write1                                                   ; full_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_byteenablen[3]~reg0  ; connector_pll:inst2|altpll:altpll_component|_clk0 ; connector_pll:inst2|altpll:altpll_component|_clk0 ; 20.000 ns                   ; 19.400 ns                 ; 14.615 ns               ;
; 4.786 ns                                ; 65.73 MHz ( period = 15.214 ns )                           ; full_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|internal_cpu_instruction_master_read_data_valid_sdram_s1_shift_register[3]       ; full_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_byteenablen[3]~reg0  ; connector_pll:inst2|altpll:altpll_component|_clk0 ; connector_pll:inst2|altpll:altpll_component|_clk0 ; 20.000 ns                   ; 19.460 ns                 ; 14.674 ns               ;
; 4.825 ns                                ; 65.90 MHz ( period = 15.175 ns )                           ; full_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|internal_cpu_instruction_master_read_data_valid_sdram_s1_shift_register[0]       ; full_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|select_n_to_the_ext_ram~reg0     ; connector_pll:inst2|altpll:altpll_component|_clk0 ; connector_pll:inst2|altpll:altpll_component|_clk0 ; 20.000 ns                   ; 19.368 ns                 ; 14.543 ns               ;
; 4.878 ns                                ; 66.13 MHz ( period = 15.122 ns )                           ; full_1c20:inst|cpu:the_cpu|internal_d_address[23]                                                                                ; full_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_byteenablen[3]~reg0  ; connector_pll:inst2|altpll:altpll_component|_clk0 ; connector_pll:inst2|altpll:altpll_component|_clk0 ; 20.000 ns                   ; 19.456 ns                 ; 14.578 ns               ;
; 4.887 ns                                ; 66.17 MHz ( period = 15.113 ns )                           ; full_1c20:inst|cpu:the_cpu|internal_d_address[17]                                                                                ; full_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_byteenablen[3]~reg0  ; connector_pll:inst2|altpll:altpll_component|_clk0 ; connector_pll:inst2|altpll:altpll_component|_clk0 ; 20.000 ns                   ; 19.406 ns                 ; 14.519 ns               ;
; 4.900 ns                                ; 66.23 MHz ( period = 15.100 ns )                           ; full_1c20:inst|cpu:the_cpu|internal_d_address[21]                                                                                ; full_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_byteenablen[3]~reg0  ; connector_pll:inst2|altpll:altpll_component|_clk0 ; connector_pll:inst2|altpll:altpll_component|_clk0 ; 20.000 ns                   ; 19.406 ns                 ; 14.506 ns               ;
; 4.927 ns                                ; 66.34 MHz ( period = 15.073 ns )                           ; full_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|internal_cpu_instruction_master_read_data_valid_sdram_s1_shift_register[0]       ; full_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_byteenablen[3]~reg0  ; connector_pll:inst2|altpll:altpll_component|_clk0 ; connector_pll:inst2|altpll:altpll_component|_clk0 ; 20.000 ns                   ; 19.460 ns                 ; 14.533 ns               ;
; 4.942 ns                                ; 66.41 MHz ( period = 15.058 ns )                           ; full_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|internal_cpu_instruction_master_read_data_valid_sdram_s1_shift_register[1]       ; full_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|select_n_to_the_ext_ram~reg0     ; connector_pll:inst2|altpll:altpll_component|_clk0 ; connector_pll:inst2|altpll:altpll_component|_clk0 ; 20.000 ns                   ; 19.368 ns                 ; 14.426 ns               ;
; 5.000 ns                                ; 66.67 MHz ( period = 15.000 ns )                           ; full_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|internal_cpu_instruction_master_read_data_valid_sdram_s1_shift_register[3]       ; full_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_ram~reg0       ; connector_pll:inst2|altpll:altpll_component|_clk0 ; connector_pll:inst2|altpll:altpll_component|_clk0 ; 20.000 ns                   ; 19.368 ns                 ; 14.368 ns               ;
; 5.044 ns                                ; 66.86 MHz ( period = 14.956 ns )                           ; full_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|internal_cpu_instruction_master_read_data_valid_sdram_s1_shift_register[1]       ; full_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_byteenablen[3]~reg0  ; connector_pll:inst2|altpll:altpll_component|_clk0 ; connector_pll:inst2|altpll:altpll_component|_clk0 ; 20.000 ns                   ; 19.460 ns                 ; 14.416 ns               ;
; 5.047 ns                                ; 66.88 MHz ( period = 14.953 ns )                           ; full_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|internal_cpu_instruction_master_read_data_valid_sdram_s1_shift_register[6]       ; full_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|select_n_to_the_ext_ram~reg0     ; connector_pll:inst2|altpll:altpll_component|_clk0 ; connector_pll:inst2|altpll:altpll_component|_clk0 ; 20.000 ns                   ; 19.368 ns                 ; 14.321 ns               ;

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