full_1c20.vhd

一个毕业设计

                 signal cpu_instruction_master_qualified_request_cpu_jtag_debug_module : IN STD_LOGIC;
                 signal cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port : IN STD_LOGIC;
                 signal cpu_instruction_master_qualified_request_ext_flash_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_qualified_request_ext_ram_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_qualified_request_lan91c111_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_qualified_request_sdram_s1 : IN STD_LOGIC;
                 signal cpu_jtag_debug_module_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal d1_button_pio_s1_end_xfer : IN STD_LOGIC;
                 signal d1_cpu_data_master_granted_cpu_jtag_debug_module : IN STD_LOGIC;
                 signal d1_cpu_data_master_granted_epcs_controller_epcs_control_port : IN STD_LOGIC;
                 signal d1_cpu_data_master_granted_ext_flash_s1 : IN STD_LOGIC;
                 signal d1_cpu_data_master_granted_ext_ram_s1 : IN STD_LOGIC;
                 signal d1_cpu_data_master_granted_lan91c111_s1 : IN STD_LOGIC;
                 signal d1_cpu_data_master_granted_sdram_s1 : IN STD_LOGIC;
                 signal d1_cpu_jtag_debug_module_end_xfer : IN STD_LOGIC;
                 signal d1_dma_control_port_slave_end_xfer : IN STD_LOGIC;
                 signal d1_epcs_controller_epcs_control_port_end_xfer : IN STD_LOGIC;
                 signal d1_ext_ram_bus_avalon_slave_end_xfer : IN STD_LOGIC;
                 signal d1_high_res_timer_s1_end_xfer : IN STD_LOGIC;
                 signal d1_irq_from_the_lan91c111 : IN STD_LOGIC;
                 signal d1_jtag_uart_avalon_jtag_slave_end_xfer : IN STD_LOGIC;
                 signal d1_lcd_display_control_slave_end_xfer : IN STD_LOGIC;
                 signal d1_led_pio_s1_end_xfer : IN STD_LOGIC;
                 signal d1_reconfig_request_pio_s1_end_xfer : IN STD_LOGIC;
                 signal d1_sdram_s1_end_xfer : IN STD_LOGIC;
                 signal d1_seven_seg_pio_s1_end_xfer : IN STD_LOGIC;
                 signal d1_sys_clk_timer_s1_end_xfer : IN STD_LOGIC;
                 signal d1_sysid_control_slave_end_xfer : IN STD_LOGIC;
                 signal d1_uart1_s1_end_xfer : IN STD_LOGIC;
                 signal d2_reset_n : IN STD_LOGIC;
                 signal dma_control_port_slave_irq_from_sa : IN STD_LOGIC;
                 signal dma_control_port_slave_readdata_from_sa : IN STD_LOGIC_VECTOR (24 DOWNTO 0);
                 signal dma_read_master_qualified_request_ext_flash_s1 : IN STD_LOGIC;
                 signal dma_read_master_qualified_request_ext_ram_s1 : IN STD_LOGIC;
                 signal dma_read_master_qualified_request_lan91c111_s1 : IN STD_LOGIC;
                 signal dma_read_master_qualified_request_sdram_s1 : IN STD_LOGIC;
                 signal dma_read_master_s_turn_at_ext_flash_s1 : IN STD_LOGIC;
                 signal dma_read_master_s_turn_at_ext_ram_s1 : IN STD_LOGIC;
                 signal dma_read_master_s_turn_at_lan91c111_s1 : IN STD_LOGIC;
                 signal dma_read_master_s_turn_at_sdram_s1 : IN STD_LOGIC;
                 signal dma_write_master_qualified_request_ext_flash_s1 : IN STD_LOGIC;
                 signal dma_write_master_qualified_request_ext_ram_s1 : IN STD_LOGIC;
                 signal dma_write_master_qualified_request_lan91c111_s1 : IN STD_LOGIC;
                 signal dma_write_master_qualified_request_sdram_s1 : IN STD_LOGIC;
                 signal dma_write_master_s_turn_at_ext_flash_s1 : IN STD_LOGIC;
                 signal dma_write_master_s_turn_at_ext_ram_s1 : IN STD_LOGIC;
                 signal dma_write_master_s_turn_at_lan91c111_s1 : IN STD_LOGIC;
                 signal dma_write_master_s_turn_at_sdram_s1 : IN STD_LOGIC;
                 signal epcs_controller_epcs_control_port_irq_from_sa : IN STD_LOGIC;
                 signal epcs_controller_epcs_control_port_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal ext_flash_s1_wait_counter_eq_0 : IN STD_LOGIC;
                 signal ext_flash_s1_wait_counter_eq_1 : IN STD_LOGIC;
                 signal high_res_timer_s1_irq_from_sa : IN STD_LOGIC;
                 signal high_res_timer_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal incoming_ext_ram_bus_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal incoming_ext_ram_bus_data_with_Xs_converted_to_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal jtag_uart_avalon_jtag_slave_irq_from_sa : IN STD_LOGIC;
                 signal jtag_uart_avalon_jtag_slave_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal jtag_uart_avalon_jtag_slave_waitrequest_from_sa : IN STD_LOGIC;
                 signal lan91c111_s1_wait_counter_eq_0 : IN STD_LOGIC;
                 signal lcd_display_control_slave_readdata_from_sa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal lcd_display_control_slave_wait_counter_eq_0 : IN STD_LOGIC;
                 signal lcd_display_control_slave_wait_counter_eq_1 : IN STD_LOGIC;
                 signal reconfig_request_pio_s1_readdata_from_sa : IN STD_LOGIC;
                 signal registered_cpu_data_master_read_data_valid_ext_flash_s1 : IN STD_LOGIC;
                 signal registered_cpu_data_master_read_data_valid_ext_ram_s1 : IN STD_LOGIC;
                 signal registered_cpu_data_master_read_data_valid_lan91c111_s1 : IN STD_LOGIC;
                 signal sdram_s1_posted_fifo_readenable : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
                 signal sdram_s1_posted_fifo_writenable : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
                 signal sdram_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal sdram_s1_waitrequest_from_sa : IN STD_LOGIC;
                 signal sys_clk_timer_s1_irq_from_sa : IN STD_LOGIC;
                 signal sys_clk_timer_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal sysid_control_slave_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal uart1_s1_irq_from_sa : IN STD_LOGIC;
                 signal uart1_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

              -- outputs:
                 signal cpu_data_master_address_to_slave : OUT STD_LOGIC_VECTOR (24 DOWNTO 0);
                 signal cpu_data_master_dbs_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal cpu_data_master_dbs_write_8 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal cpu_data_master_irq : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal cpu_data_master_no_byte_enables_and_last_term : OUT STD_LOGIC;
                 signal cpu_data_master_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal cpu_data_master_waitrequest : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of cpu_data_master_arbitrator : entity is FALSE;
end entity cpu_data_master_arbitrator;


architecture europa of cpu_data_master_arbitrator is
                signal cpu_data_master_dbs_increment :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal dbs_8_reg_segment_0 :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal dbs_8_reg_segment_1 :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal dbs_8_reg_segment_2 :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal dbs_count_enable :  STD_LOGIC;
                signal dbs_counter_overflow :  STD_LOGIC;
                signal dummy_sink :  STD_LOGIC;
                signal internal_cpu_data_master_address_to_slave :  STD_LOGIC_VECTOR (24 DOWNTO 0);
                signal internal_cpu_data_master_dbs_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal internal_cpu_data_master_no_byte_enables_and_last_term :  STD_LOGIC;
                signal internal_cpu_data_master_waitrequest :  STD_LOGIC;
                signal last_dbs_term_and_run :  STD_LOGIC;
                signal next_dbs_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal p1_cpu_data_master_waitrequest :  STD_LOGIC;
                signal p1_dbs_8_reg_segment_0 :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal p1_dbs_8_reg_segment_1 :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal p1_dbs_8_reg_segment_2 :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal p1_registered_cpu_data_master_readdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal pre_dbs_count_enable :  STD_LOGIC;
                signal r_0 :  STD_LOGIC;
                signal r_1 :  STD_LOGIC;
                signal r_2 :  STD_LOGIC;
                signal r_3 :  STD_LOGIC;
                signal r_4 :  STD_LOGIC;
                signal registered_cpu_data_master_readdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);

begin

  --r_0 cascaded wait assignment, which is an e_assign
  r_0 <= Vector_To_Std_Logic(((((((((((((((((((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_data_master_qualified_request_button_pio_s1 OR NOT cpu_data_master_requests_button_pio_s1))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_data_master_qualified_request_button_pio_s1 OR NOT cpu_data_master_read)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_data_master_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_data_master_qualified_request_button_pio_s1 OR NOT cpu_data_master_write)))) OR ((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_data_master_write)))))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((NOT(cpu_data_master_qualified_request_cpu_jtag_debug_module) OR ((cpu_data_master_qualified_request_cpu_jtag_debug_module AND ((NOT(cpu_instruction_master_qualified_request_cpu_jtag_debug_module) OR ((cpu_instruction_master_qualified_request_cpu_jtag_debug_module AND (A_WE_StdLogic((std_logic'((d1_cpu_jtag_debug_module_end_xfer)) = '1'), cpu_data_master_s_turn_at_cpu_jtag_debug_module, d1_cpu_data_master_granted_cpu_jtag_debug_module)))))))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_data_master_qualified_request_cpu_jtag_debug_module OR NOT cpu_data_master_read)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_data_master_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_data_master_qualified_request_cpu_jtag_debug_module OR NOT cpu_data_master_write)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_data_master_write)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_data_master_qualified_request_dma_control_port_slave OR NOT cpu_data_master_read)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_data_master_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_data_master_qualified_request_dma_control_port_slave OR NOT cpu_data_master_write)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_data_master_write)))))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((NOT(cpu_data_master_qualified_request_epcs_controller_epcs_control_port) OR ((cpu_data_master_qualified_request_epcs_controller_epcs_control_port AND ((NOT(cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port) OR ((cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port AND (A_WE_StdLogic((std_logic'((d1_epcs_controller_epcs_control_port_end_xfer)) = '1'), cpu_data_master_s_turn_at_epcs_controller_epcs_control_port, d1_cpu_data_master_granted_epcs_controller_epcs_control_port)))))))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_data_master_qualified_request_epcs_controller_epcs_control_port OR NOT cpu_data_master_read)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_data_master_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_data_master_qualified_request_epcs_controller_epcs_control_port OR NOT cpu_data_master_write)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_data_master_write)))))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((((cpu_data_master_qualified_request_lan91c111_s1 OR registered_cpu_data_master_read_data_valid_lan91c111_s1) OR NOT cpu_data_master_requests_lan91c111_s1)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((((cpu_data_master_qualified_request_ext_flash_s1 OR (((registered_cpu_data_master_read_data_valid_ext_flash_s1 AND internal_cpu_data_master_dbs_address(1)) AND internal_cpu_data_master_dbs_address(0)))) OR ((((cpu_data_master_write AND NOT(cpu_data_master_byteenable_ext_flash_s1)) AND internal_cpu_data_master_dbs_address(1)) AND internal_cpu_data_master_dbs_address(0)))) OR NOT cpu_data_master_requests_ext_flash_s1)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((((cpu_data_master_qualified_request_ext_ram_s1 OR registered_cpu_data_master_read_data_valid_ext_ram_s1) OR NOT cpu_data_master_requests_ext_ram_s1)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((NOT(cpu_data_master_qualified_request_lan91c111_s1) OR ((cpu_data_master_qualified_request_lan91c111_s1 AND ((NOT(dma_write_master_qualified_request_lan91c111_s1) OR ((dma_write_master_qualified_request_lan91c111_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), (NOT(dma_write_master_s_turn_at_lan91c111_s1)), d1_cpu_data_master_granted_lan91c111_s1)))))))))))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((NOT(cpu_data_master_qualified_request_ext_flash_s1) OR ((cpu_data_master_qualified_request_ext_flash_s1 AND ((NOT(dma_write_master_qualified_request_lan91c111_s1) OR ((dma_write_master_qualified_request_lan91c111_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), (NOT(dma_write_master_s_turn_at_lan91c111_s1)), d1_cpu_data_master_granted_ext_flash_s1)))))))))))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((NOT(cpu_data_master_qualified_request_ext_ram_s1) OR ((cpu_data_master_qualified_request_ext_ram_s1 AND ((NOT(dma_write_master_qualified_request_lan91c111_s1) OR ((dma_write_master_qualified_request_lan91c111_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), (NOT(dma_write_master_s_turn_at_lan91c111_s1)), d1_cpu_data_master_granted_ext_ram_s1)))))))))))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((NOT(cpu_data_master_qualified_request_lan91c111_s1) OR ((cpu_data_master_qualified_request_lan91c111_s1 AND ((NOT(dma_write_master_qualified_request_ext_flash_s1) OR ((dma_write_master_qualified_request_ext_flash_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), (NOT(dma_write_master_s_turn_at_ext_flash_s1)), d1_cpu_data_master_granted_lan91c111_s1)))))))))))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((NOT(cpu_data_master_qualified_request_ext_flash_s1) OR ((cpu_data_master_qualified_request_ext_flash_s1 AND ((NOT(dma_write_master_qualified_request_ext_flash_s1) OR ((dma_write_master_qualified_request_ext_flash_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), (NOT(dma_write_master_s_turn_at_ext_flash_s1)), d1_cpu_data_master_granted_ext_flash_s1)))))))))))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((NOT(cpu_data_master_qualified_request_ext_ram_s1) OR ((cpu_data_master_qualified_request_ext_ram_s1 AND ((NOT(dma_write_master_qualified_request_ext_flash_s1) OR ((dma_write_master_qualified_request_ext_flash_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), (NOT(dma_write_master_s_turn_at_ext_flash_s1)), d1_cpu_data_master_granted_ext_ram_s1)))))))))))))));
  --cascaded wait assignment, which is an e_assign
  p1_cpu_data_master_waitrequest <= NOT (((((r_0 AND r_1) AND r_2) AND r_3) AND r_4));
  --r_1 cascaded wait assignment, which is an e_assign
  r_1 <= ((((((((((((NOT(cpu_data_master_qualified_request_lan91c111_s1) OR ((cpu_data_master_qualified_request_lan91c111_s1 AND ((NOT(dma_write_master_qualified_request_ext_ram_s1) OR ((dma_write_master_qualified_request_ext_ram_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), (NOT(dma_write_master_s_turn_at_ext_ram_s1)), d1_cpu_data_master_granted_lan91c111_s1)))))))))) AND ((NOT(cpu_data_master_qualified_request_ext_flash_s1) OR ((cpu_data_master_qualified_request_ext_flash_s1 AND ((NOT(dma_write_master_qualified_request_ext_ram_s1) OR ((dma_write_master_qualified_request_ext_ram_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), (NOT(dma_write_master_s_turn_at_ext_ram_s1)), d1_cpu_data_master_granted_ext_flash_s1))))))))))) AND ((NOT(cpu_data_master_qualified_request_ext_ram_s1) OR ((cpu_data_master_qualified_request_ext_ram_s1 AND ((NOT(dma_write_master_qualified_request_ext_ram_s1) OR ((dma_write_master_qualified_request_ext_ram_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), (NOT(dma_write_master_s_turn_at_ext_ram_s1)), d1_cpu_data_master_granted_ext_ram_s1))))))))))) AND ((NOT(cpu_data_master_qualified_request_lan91c111_s1) OR ((cpu_data_master_qualified_request_lan91c111_s1 AND ((NOT(dma_read_master_qualified_request_lan91c111_s1) OR ((dma_read_master_qualified_request_lan91c111_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), (NOT(dma_read_master_s_turn_at_lan91c111_s1)), d1_cpu_data_master_granted_lan91c111_s1))))))))))) AND ((NOT(cpu_data_master_qualified_request_ext_flash_s1) OR ((cpu_data_master_qualified_request_ext_flash_s1 AND ((NOT(dma_read_master_qualified_request_lan91c111_s1) OR ((dma_read_master_qualified_request_lan91c111_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), (NOT(dma_read_master_s_turn_at_lan91c111_s1)), d1_cpu_data_master_granted_ext_flash_s1))))))))))) AND ((NOT(cpu_data_master_qualified_request_ext_ram_s1) OR ((cpu_data_master_qualified_request_ext_ram_s1 AND ((NOT(dma_read_master_qualified_request_lan91c111_s1) OR ((dma_read_master_qualified_request_lan91c111_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), (NOT(dma_read_master_s_turn_at_lan91c111_s1)), d1_cpu_data_master_granted_ext_ram_s1))))))))))) AND ((NOT(cpu_data_master_qualified_request_lan91c111_s1) OR ((cpu_data_master_qualified_request_lan91c111_s1 AND ((NOT(dma_read_master_qualified_request_ext_flash_s1) OR ((dma_read_master_qualified_request_ext_flash_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), (NOT(dma_read_master_s_turn_at_ext_flash_s1)), d1_cpu_data_master_granted_lan91c111_s1))))))))))) AND ((NOT(cpu_data_master_qualified_request_ext_flash_s1) OR ((cpu_data_master_qualified_request_ext_flash_s1 AND ((NOT(dma_read_master_qualified_request_ext_flash_s1) OR ((dma_read_master_qualified_request_ext_flash_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), (NOT(dma_read_master_s_turn_at_ext_flash_s1)), d1_cpu_data_master_granted_ext_flash_s1))))))))))) AND ((NOT(cpu_data_master_qualified_request_ext_ram_s1) OR ((cpu_data_master_qualified_request_ext_ram_s1 AND ((NOT(dma_read_master_qualified_request_ext_flash_s1) OR ((dma_read_master_qualified_request_ext_flash_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), (NOT(dma_read_master_s_turn_at_ext_flash_s1)), d1_cpu_data_master_granted_ext_ram_s1))))))))))) AND ((NOT(cpu_data_master_qualified_request_lan91c111_s1) OR ((cpu_data_master_qualified_request_lan91c111_s1 AND ((NOT(dma_read_master_qualified_request_ext_ram_s1) OR ((dma_read_master_qualified_request_ext_ram_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), (NOT(dma_read_master_s_turn_at_ext_ram_s1)), d1_cpu_data_master_granted_lan91c111_s1))))))))))) AND ((NOT(cpu_data_master_qualified_request_ext_flash_s1) OR ((cpu_data_master_qualified_request_ext_flash_s1 AND ((NOT(dma_read_master_qualified_request_ext_ram_s1) OR ((dma_read_master_qualified_request_ext_ram_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), (NOT(dma_read_master_s_turn_at_ext_ram_s1)), d1_cpu_data_master_granted_ext_flash_s1))))))))))) AND ((NOT(cpu_data_master_qualified_request_ext_ram_s1) OR ((cpu_data_master_qualified_request_ext_ram_s1 AND ((NOT(dma_read_master_qualified_request_ext_ram_s1) OR ((dma_read_master_qualified_request_ext_ram_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), (NOT(dma_read_master_s_turn_at_ext_ram_s1)), d1_cpu_data_master_granted_ext_ram_s1))))))))));
  --r_2 cascaded wait assignment, which is an e_assign
  r_2 <= Vector_To_Std_Logic((((((((((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((((((((((((NOT(cpu_data_master_qualified_request_lan91c111_s1) OR ((cpu_data_master_qualified_request_lan91c111_s1 AND ((NOT(cpu_instruction_master_qualified_request_lan91c111_s1) OR ((cpu_instruction_master_qualified_request_lan91c111_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), cpu_data_master_s_turn_at_lan91c111_s1, d1_cpu_data_master_granted_lan91c111_s1)))))))))) AND ((NOT(cpu_data_master_qualified_request_lan91c111_s1) OR ((cpu_data_master_qualified_request_lan91c111_s1 AND ((NOT(cpu_instruction_master_qualified_request_ext_flash_s1) OR ((cpu_instruction_master_qualified_request_ext_flash_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), cpu_data_master_s_turn_at_lan91c111_s1, d1_cpu_data_master_granted_lan91c111_s1))))))))))) AND ((NOT(cpu_data_master_qualified_request_lan91c111_s1) OR ((cpu_data_master_qualified_request_lan91c111_s1 AND ((NOT(cpu_instruction_master_qualified_request_ext_ram_s1) OR ((cpu_instruction_master_qualified_request_ext_ram_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), cpu_data_master_s_turn_at_lan91c111_s1, d1_cpu_data_master_granted_lan91c111_s1))))))))))) AND ((NOT(cpu_data_master_qualified_request_ext_flash_s1) OR ((cpu_data_master_qualified_request_ext_flash_s1 AND ((NOT(cpu_instruction_master_qualified_request_lan91c111_s1) OR ((cpu_instruction_master_qualified_request_lan91c111_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), cpu_data_master_s_turn_at_ext_flash_s1, d1_cpu_data_master_granted_ext_flash_s1))))))))))) AND ((NOT(cpu_data_master_qualified_request_ext_flash_s1) OR ((cpu_data_master_qualified_request_ext_flash_s1 AND ((NOT(cpu_instruction_master_qualified_request_ext_flash_s1) OR ((cpu_instruction_master_qualified_request_ext_flash_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), cpu_data_master_s_turn_at_ext_flash_s1, d1_cpu_data_master_granted_ext_flash_s1))))))))))) AND ((NOT(cpu_data_master_qualified_request_ext_flash_s1) OR ((cpu_data_master_qualified_request_ext_flash_s1 AND ((NOT(cpu_instruction_master_qualified_request_ext_ram_s1) OR ((cpu_instruction_master_qualified_request_ext_ram_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), cpu_data_master_s_turn_at_ext_flash_s1, d1_cpu_data_master_granted_ext_flash_s1))))))))))) AND ((NOT(cpu_data_master_qualified_request_ext_ram_s1) OR ((cpu_data_master_qualified_request_ext_ram_s1 AND ((NOT(cpu_instruction_master_qualified_request_lan91c111_s1) OR ((cpu_instruction_master_qualified_request_lan91c111_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), cpu_data_master_s_turn_at_ext_ram_s1, d1_cpu_data_master_granted_ext_ram_s1))))))))))) AND ((NOT(cpu_data_master_qualified_request_ext_ram_s1) OR ((cpu_data_master_qualified_request_ext_ram_s1 AND ((NOT(cpu_instruction_master_qualified_request_ext_flash_s1) OR ((cpu_instruction_master_qualified_request_ext_flash_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), cpu_data_master_s_turn_at_ext_ram_s1, d1_cpu_data_master_granted_ext_ram_s1))))))))))) AND ((NOT(cpu_data_master_qualified_request_ext_ram_s1) OR ((cpu_data_master_qualified_request_ext_ram_s1 AND ((NOT(cpu_instruction_master_qualified_request_ext_ram_s1) OR ((cpu_instruction_master_qualified_request_ext_ram_s1 AND (A_WE_StdLogic((std_logic'((d1_ext_ram_bus_avalon_slave_end_xfer)) = '1'), cpu_data_master_s_turn_at_ext_ram_s1, d1_cpu_data_master_granted_ext_ram_s1))))))))))) AND (((NOT cpu_data_master_qualified_request_lan91c111_s1 OR NOT cpu_data_master_read) OR ((registered_cpu_data_master_read_data_valid_lan91c111_s1 AND cpu_data_master_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_data_master_qualified_request_lan91c111_s1 OR NOT cpu_data_master_write)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT d1_ext_ram_bus_avalon_slave_end_xfer)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_data_master_write)))))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((((NOT cpu_data_master_qualified_request_ext_flash_s1 OR NOT cpu_data_master_read) OR (((registered_cpu_data_master_read_data_valid_ext_flash_s1 AND ((internal_cpu_data_master_dbs_address(1) AND internal_cpu_data_master_dbs_address(0)))) AND cpu_data_master_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_data_master_qualified_request_ext_flash_s1 OR NOT cpu_data_master_write)))) OR ((((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(ext_flash_s1_wait_counter_eq_1)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((internal_cpu_data_master_dbs_address(1) AND internal_cpu_data_master_dbs_address(0))))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_data_master_write)))))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((((NOT cpu_data_master_qualified_request_ext_ram_s1 OR NOT cpu_data_master_read) OR ((registered_cpu_data_master_read_data_valid_ext_ram_s1 AND cpu_data_master_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_data_master_qualified_request_ext_ram_s1 OR NOT cpu_data_master_write)))) OR ((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_data_master_write)))))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_data_master_qualified_request_high_res_timer_s1 OR NOT cpu_data_master_requests_high_res_timer_s1)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_data_master_qualified_request_high_res_timer_s1 OR NOT cpu_data_master_read)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_data_master_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_data_master_qualified_request_high_res_timer_s1 OR NOT cpu_data_master_write)))) OR ((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_data_master_write)))))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave OR NOT cpu_data_master_requests_jtag_uart_avalon_jtag_slave)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave OR NOT cpu_data_master_read)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT jtag_uart_avalon_jtag_slave_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_data_master_read)))))))));
  --r_3 cascaded wait assignment, which is an e_assign
  r_3 <= Vector_To_Std_Logic(((((((((((((((((((((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave OR NOT cpu_data_master_write)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT jtag_uart_avalon_jtag_slave_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_data_master_write))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_data_master_qualified_request_lcd_display_control_slave OR NOT cpu_data_master_read)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(lcd_display_control_slave_wait_counter_eq_1)))) AND (std_logic_vector'("000000000000000000000