full_1c20.vhd

一个毕业设计

  cpu_instruction_master_requests_cpu_jtag_debug_module <= internal_cpu_instruction_master_requests_cpu_jtag_debug_module;
  --vhdl renameroo for output signals
  d1_cpu_data_master_granted_cpu_jtag_debug_module <= internal_d1_cpu_data_master_granted_cpu_jtag_debug_module;
  --vhdl renameroo for output signals
  d1_cpu_instruction_master_granted_cpu_jtag_debug_module <= internal_d1_cpu_instruction_master_granted_cpu_jtag_debug_module;
  --vhdl renameroo for output signals
  d1_cpu_jtag_debug_module_end_xfer <= internal_d1_cpu_jtag_debug_module_end_xfer;

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity cpu_custom_instruction_master_arbitrator is 
        port (
              -- inputs:
                 signal bswap_cpu_s1_result_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal d2_reset_n : IN STD_LOGIC;

              -- outputs:
                 signal bswap_cpu_s1_select : OUT STD_LOGIC;
                 signal cpu_custom_instruction_master_combo_result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal cpu_custom_instruction_master_reset_n : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of cpu_custom_instruction_master_arbitrator : entity is FALSE;
end entity cpu_custom_instruction_master_arbitrator;


architecture europa of cpu_custom_instruction_master_arbitrator is
                signal internal_bswap_cpu_s1_select :  STD_LOGIC;

begin

  --cpu_custom_instruction_master_combo_result mux, which is an e_mux
  cpu_custom_instruction_master_combo_result <= A_REP(internal_bswap_cpu_s1_select, 32) AND bswap_cpu_s1_result_from_sa;
  --cpu_custom_instruction_master_reset_n local reset_n, which is an e_assign
  cpu_custom_instruction_master_reset_n <= d2_reset_n;
  internal_bswap_cpu_s1_select <= std_logic'('1');
  --vhdl renameroo for output signals
  bswap_cpu_s1_select <= internal_bswap_cpu_s1_select;

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity cpu_data_master_arbitrator is 
        port (
              -- inputs:
                 signal button_pio_s1_irq_from_sa : IN STD_LOGIC;
                 signal button_pio_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal clk : IN STD_LOGIC;
                 signal cpu_data_master_address : IN STD_LOGIC_VECTOR (24 DOWNTO 0);
                 signal cpu_data_master_byteenable_ext_flash_s1 : IN STD_LOGIC;
                 signal cpu_data_master_debugaccess : IN STD_LOGIC;
                 signal cpu_data_master_granted_button_pio_s1 : IN STD_LOGIC;
                 signal cpu_data_master_granted_cpu_jtag_debug_module : IN STD_LOGIC;
                 signal cpu_data_master_granted_dma_control_port_slave : IN STD_LOGIC;
                 signal cpu_data_master_granted_epcs_controller_epcs_control_port : IN STD_LOGIC;
                 signal cpu_data_master_granted_ext_flash_s1 : IN STD_LOGIC;
                 signal cpu_data_master_granted_ext_ram_s1 : IN STD_LOGIC;
                 signal cpu_data_master_granted_high_res_timer_s1 : IN STD_LOGIC;
                 signal cpu_data_master_granted_jtag_uart_avalon_jtag_slave : IN STD_LOGIC;
                 signal cpu_data_master_granted_lan91c111_s1 : IN STD_LOGIC;
                 signal cpu_data_master_granted_lcd_display_control_slave : IN STD_LOGIC;
                 signal cpu_data_master_granted_led_pio_s1 : IN STD_LOGIC;
                 signal cpu_data_master_granted_reconfig_request_pio_s1 : IN STD_LOGIC;
                 signal cpu_data_master_granted_sdram_s1 : IN STD_LOGIC;
                 signal cpu_data_master_granted_seven_seg_pio_s1 : IN STD_LOGIC;
                 signal cpu_data_master_granted_sys_clk_timer_s1 : IN STD_LOGIC;
                 signal cpu_data_master_granted_sysid_control_slave : IN STD_LOGIC;
                 signal cpu_data_master_granted_uart1_s1 : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_button_pio_s1 : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_cpu_jtag_debug_module : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_dma_control_port_slave : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_epcs_controller_epcs_control_port : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_ext_flash_s1 : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_ext_ram_s1 : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_high_res_timer_s1 : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_lan91c111_s1 : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_lcd_display_control_slave : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_led_pio_s1 : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_reconfig_request_pio_s1 : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_sdram_s1 : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_seven_seg_pio_s1 : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_sys_clk_timer_s1 : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_sysid_control_slave : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_uart1_s1 : IN STD_LOGIC;
                 signal cpu_data_master_read : IN STD_LOGIC;
                 signal cpu_data_master_read_data_valid_ext_flash_s1 : IN STD_LOGIC;
                 signal cpu_data_master_read_data_valid_ext_ram_s1 : IN STD_LOGIC;
                 signal cpu_data_master_read_data_valid_lan91c111_s1 : IN STD_LOGIC;
                 signal cpu_data_master_read_data_valid_sdram_s1 : IN STD_LOGIC;
                 signal cpu_data_master_read_data_valid_sdram_s1_shift_register : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
                 signal cpu_data_master_requests_button_pio_s1 : IN STD_LOGIC;
                 signal cpu_data_master_requests_cpu_jtag_debug_module : IN STD_LOGIC;
                 signal cpu_data_master_requests_dma_control_port_slave : IN STD_LOGIC;
                 signal cpu_data_master_requests_epcs_controller_epcs_control_port : IN STD_LOGIC;
                 signal cpu_data_master_requests_ext_flash_s1 : IN STD_LOGIC;
                 signal cpu_data_master_requests_ext_ram_s1 : IN STD_LOGIC;
                 signal cpu_data_master_requests_high_res_timer_s1 : IN STD_LOGIC;
                 signal cpu_data_master_requests_jtag_uart_avalon_jtag_slave : IN STD_LOGIC;
                 signal cpu_data_master_requests_lan91c111_s1 : IN STD_LOGIC;
                 signal cpu_data_master_requests_lcd_display_control_slave : IN STD_LOGIC;
                 signal cpu_data_master_requests_led_pio_s1 : IN STD_LOGIC;
                 signal cpu_data_master_requests_reconfig_request_pio_s1 : IN STD_LOGIC;
                 signal cpu_data_master_requests_sdram_s1 : IN STD_LOGIC;
                 signal cpu_data_master_requests_seven_seg_pio_s1 : IN STD_LOGIC;
                 signal cpu_data_master_requests_sys_clk_timer_s1 : IN STD_LOGIC;
                 signal cpu_data_master_requests_sysid_control_slave : IN STD_LOGIC;
                 signal cpu_data_master_requests_uart1_s1 : IN STD_LOGIC;
                 signal cpu_data_master_s_turn_at_cpu_jtag_debug_module : IN STD_LOGIC;
                 signal cpu_data_master_s_turn_at_epcs_controller_epcs_control_port : IN STD_LOGIC;
                 signal cpu_data_master_s_turn_at_ext_flash_s1 : IN STD_LOGIC;
                 signal cpu_data_master_s_turn_at_ext_ram_s1 : IN STD_LOGIC;
                 signal cpu_data_master_s_turn_at_lan91c111_s1 : IN STD_LOGIC;
                 signal cpu_data_master_s_turn_at_sdram_s1 : IN STD_LOGIC;
                 signal cpu_data_master_write : IN STD_LOGIC;
                 signal cpu_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);