h8300.h

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/* Definitions of target machine for GNU compiler.
   Renesas H8/300 (generic)
   Copyright (C) 1992, 1993, 1994, 1995, 1996, 1996, 1997, 1998, 1999,
   2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
   Contributed by Steve Chamberlain ([e-mail]),
   Jim Wilson ([e-mail]), and Doug Evans ([e-mail]).

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING.  If not, write to
the Free Software Foundation, 51 Franklin Street, Fifth Floor,
Boston, MA 02110-1301, USA.  */

#ifndef GCC_H8300_H
#define GCC_H8300_H

/* Which CPU to compile for.
   We use int for CPU_TYPE to avoid lots of casts.  */
#if 0 /* defined in insn-attr.h, here for documentation */
enum attr_cpu { CPU_H8300, CPU_H8300H };
#endif
extern int cpu_type;

/* Various globals defined in h8300.c.  */

extern const char *h8_push_op, *h8_pop_op, *h8_mov_op;
extern const char * const *h8_reg_names;

/* Target CPU builtins.  */
#define TARGET_CPU_CPP_BUILTINS()			\
  do							\
    {							\
      if (TARGET_H8300H)				\
	{						\
	  builtin_define ("__H8300H__");		\
	  builtin_assert ("cpu=h8300h");		\
	  builtin_assert ("machine=h8300h");		\
	  if (TARGET_NORMAL_MODE)			\
	    {						\
	      builtin_define ("__NORMAL_MODE__");	\
	    }						\
	}						\
      else if (TARGET_H8300SX)				\
	{						\
	  builtin_define ("__H8300SX__");		\
	  if (TARGET_NORMAL_MODE)			\
	    {						\
	      builtin_define ("__NORMAL_MODE__");	\
	    }						\
	}						\
      else if (TARGET_H8300S)				\
	{						\
	  builtin_define ("__H8300S__");		\
	  builtin_assert ("cpu=h8300s");		\
	  builtin_assert ("machine=h8300s");		\
	  if (TARGET_NORMAL_MODE)			\
	    {						\
	      builtin_define ("__NORMAL_MODE__");	\
	    }						\
	}						\
      else						\
	{						\
	  builtin_define ("__H8300__");			\
	  builtin_assert ("cpu=h8300");			\
	  builtin_assert ("machine=h8300");		\
	}						\
    }							\
  while (0)

#define LINK_SPEC "%{mh:%{mn:-m h8300hn}} %{mh:%{!mn:-m h8300h}} %{ms:%{mn:-m h8300sn}} %{ms:%{!mn:-m h8300s}}"

#define LIB_SPEC "%{mrelax:-relax} %{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"

#define OPTIMIZATION_OPTIONS(LEVEL, SIZE)				 \
  do									 \
    {									 \
      /* Basic block reordering is only beneficial on targets with cache \
	 and/or variable-cycle branches where (cycle count taken !=	 \
	 cycle count not taken).  */					 \
      flag_reorder_blocks = 0;						 \
    }									 \
  while (0)

/* Print subsidiary information on the compiler version in use.  */

#define TARGET_VERSION fprintf (stderr, " (Renesas H8/300)");

/* Macros used in the machine description to test the flags.  */

/* Select between the H8/300 and H8/300H CPUs.  */
#define TARGET_H8300	(! TARGET_H8300H && ! TARGET_H8300S)
#define TARGET_H8300S	(TARGET_H8300S_1 || TARGET_H8300SX)
/* Some multiply instructions are not available in all H8SX variants.
   Use this macro instead of TARGET_H8300SX to indicate this, even
   though we don't actually generate different code for now.  */
#define TARGET_H8300SXMUL TARGET_H8300SX

#ifdef IN_LIBGCC2
#undef TARGET_H8300H
#undef TARGET_H8300S
#undef TARGET_NORMAL_MODE
/* If compiling libgcc2, make these compile time constants based on what
   flags are we actually compiling with.  */
#ifdef __H8300H__
#define TARGET_H8300H	1
#else
#define TARGET_H8300H	0
#endif
#ifdef __H8300S__
#define TARGET_H8300S	1
#else
#define TARGET_H8300S	0
#endif
#ifdef __NORMAL_MODE__
#define TARGET_NORMAL_MODE 1
#else
#define TARGET_NORMAL_MODE 0
#endif
#endif /* !IN_LIBGCC2 */

/* Do things that must be done once at start up.  */

#define OVERRIDE_OPTIONS			\
  do						\
    {						\
      h8300_init_once ();			\
    }						\
  while (0)

/* Default target_flags if no switches specified.  */

#ifndef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_QUICKCALL)
#endif

/* Show we can debug even without a frame pointer.  */
/* #define CAN_DEBUG_WITHOUT_FP */

/* Define this if addresses of constant functions
   shouldn't be put through pseudo regs where they can be cse'd.
   Desirable on machines where ordinary constants are expensive
   but a CALL with constant address is cheap.

   Calls through a register are cheaper than calls to named
   functions; however, the register pressure this causes makes
   CSEing of function addresses generally a lose.  */
#define NO_FUNCTION_CSE

/* Target machine storage layout */

/* Define this if most significant bit is lowest numbered
   in instructions that operate on numbered bit-fields.
   This is not true on the H8/300.  */
#define BITS_BIG_ENDIAN 0

/* Define this if most significant byte of a word is the lowest numbered.  */
/* That is true on the H8/300.  */
#define BYTES_BIG_ENDIAN 1

/* Define this if most significant word of a multiword number is lowest
   numbered.  */
#define WORDS_BIG_ENDIAN 1

#define MAX_BITS_PER_WORD	32

/* Width of a word, in units (bytes).  */
#define UNITS_PER_WORD		(TARGET_H8300H || TARGET_H8300S ? 4 : 2)
#define MIN_UNITS_PER_WORD	2

#define SHORT_TYPE_SIZE	16
#define INT_TYPE_SIZE		(TARGET_INT32 ? 32 : 16)
#define LONG_TYPE_SIZE		32
#define LONG_LONG_TYPE_SIZE	64
#define FLOAT_TYPE_SIZE	32
#define DOUBLE_TYPE_SIZE	32
#define LONG_DOUBLE_TYPE_SIZE	DOUBLE_TYPE_SIZE

#define MAX_FIXED_MODE_SIZE	32

/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
#define PARM_BOUNDARY (TARGET_H8300H || TARGET_H8300S ? 32 : 16)

/* Allocation boundary (in *bits*) for the code of a function.  */
#define FUNCTION_BOUNDARY 16

/* Alignment of field after `int : 0' in a structure.  */
/* One can argue this should be 32 for -mint32, but since 32 bit ints only
   need 16 bit alignment, this is left as is so that -mint32 doesn't change
   structure layouts.  */
#define EMPTY_FIELD_BOUNDARY 16

/* No data type wants to be aligned rounder than this.
   32 bit values are aligned as such on the H8/300H and H8S for speed.  */
#define BIGGEST_ALIGNMENT \
(((TARGET_H8300H || TARGET_H8300S) && ! TARGET_ALIGN_300) ? 32 : 16)

/* The stack goes in 16/32 bit lumps.  */
#define STACK_BOUNDARY (TARGET_H8300 ? 16 : 32)

/* Define this if move instructions will actually fail to work
   when given unaligned data.  */
/* On the H8/300, longs can be aligned on halfword boundaries, but not
   byte boundaries.  */
#define STRICT_ALIGNMENT 1

/* Standard register usage.  */

/* Number of actual hardware registers.
   The hardware registers are assigned numbers for the compiler
   from 0 to just below FIRST_PSEUDO_REGISTER.

   All registers that the compiler knows about must be given numbers,
   even those that are not normally considered general registers.

   Reg 9 does not correspond to any hardware register, but instead
   appears in the RTL as an argument pointer prior to reload, and is
   eliminated during reloading in favor of either the stack or frame
   pointer.  */

#define FIRST_PSEUDO_REGISTER 12

/* 1 for registers that have pervasive standard uses
   and are not available for the register allocator.  */

#define FIXED_REGISTERS				\
/* r0 r1 r2 r3 r4 r5 r6 r7 mac ap rap fp */	\
  { 0, 0, 0, 0, 0, 0, 0, 1,  0, 1,  1, 1 }

/* 1 for registers not available across function calls.
   These must include the FIXED_REGISTERS and also any
   registers that can be used without being saved.
   The latter must include the registers where values are returned
   and the register where structure-value addresses are passed.
   Aside from that, you can include as many other registers as you
   like.

   H8 destroys r0,r1,r2,r3.  */

#define CALL_USED_REGISTERS			\
/* r0 r1 r2 r3 r4 r5 r6 r7 mac ap rap fp */	\
  { 1, 1, 1, 1, 0, 0, 0, 1,  1, 1,  1, 1 }

#define REG_ALLOC_ORDER				\
/* r0 r1 r2 r3 r4 r5 r6 r7 mac ap rap  fp */	\
  { 2, 3, 0, 1, 4, 5, 6, 8,  7, 9, 10, 11 }

#define CONDITIONAL_REGISTER_USAGE			\
{							\
  if (!TARGET_MAC)					\
    fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1;	\
}

#define HARD_REGNO_NREGS(REGNO, MODE)		\
  h8300_hard_regno_nregs ((REGNO), (MODE))

#define HARD_REGNO_MODE_OK(REGNO, MODE)		\
  h8300_hard_regno_mode_ok ((REGNO), (MODE))

/* Value is 1 if it is a good idea to tie two pseudo registers
   when one has mode MODE1 and one has mode MODE2.
   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
   for any hard reg, then this must be 0 for correct output.  */
#define MODES_TIEABLE_P(MODE1, MODE2)					  \
  ((MODE1) == (MODE2)							  \
   || (((MODE1) == QImode || (MODE1) == HImode				  \
	|| ((TARGET_H8300H || TARGET_H8300S) && (MODE1) == SImode))	  \
       &&  ((MODE2) == QImode || (MODE2) == HImode			  \
	    || ((TARGET_H8300H || TARGET_H8300S) && (MODE2) == SImode))))

/* A C expression that is nonzero if hard register NEW_REG can be
   considered for use as a rename register for OLD_REG register */

#define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG)		\
   h8300_hard_regno_rename_ok (OLD_REG, NEW_REG)

/* Specify the registers used for certain standard purposes.
   The values of these macros are register numbers.  */

/* H8/300 pc is not overloaded on a register.  */

/*#define PC_REGNUM 15*/

/* Register to use for pushing function arguments.  */
#define STACK_POINTER_REGNUM SP_REG

/* Base register for access to local variables of the function.  */
#define HARD_FRAME_POINTER_REGNUM HFP_REG

/* Base register for access to local variables of the function.  */
#define FRAME_POINTER_REGNUM FP_REG

/* Value should be nonzero if functions must have frame pointers.
   Zero means the frame pointer need not be set up (and parms
   may be accessed via the stack pointer) in functions that seem suitable.
   This is computed in `reload', in reload1.c.  */
#define FRAME_POINTER_REQUIRED 0

/* Base register for access to arguments of the function.  */
#define ARG_POINTER_REGNUM AP_REG

/* Register in which static-chain is passed to a function.  */
#define STATIC_CHAIN_REGNUM SC_REG

/* Fake register that holds the address on the stack of the
   current function's return address.  */
#define RETURN_ADDRESS_POINTER_REGNUM RAP_REG

/* A C expression whose value is RTL representing the value of the return
   address for the frame COUNT steps up from the current frame.
   FRAMEADDR is already the frame pointer of the COUNT frame, assuming
   a stack layout with the frame pointer as the first saved register.  */
#define RETURN_ADDR_RTX(COUNT, FRAME) h8300_return_addr_rtx ((COUNT), (FRAME))

/* Define the classes of registers for register constraints in the
   machine description.  Also define ranges of constants.

   One of the classes must always be named ALL_REGS and include all hard regs.
   If there is more than one class, another class must be named NO_REGS
   and contain no registers.

   The name GENERAL_REGS must be the name of a class (or an alias for
   another name such as ALL_REGS).  This is the class of registers
   that is allowed by "g" or "r" in a register constraint.
   Also, registers outside this class are allocated only when
   instructions express preferences for them.

   The classes must be numbered in nondecreasing order; that is,
   a larger-numbered class must never be contained completely
   in a smaller-numbered class.

   For any two classes, it is very desirable that there be another
   class that represents their union.  */

enum reg_class {
  NO_REGS, COUNTER_REGS, SOURCE_REGS, DESTINATION_REGS,
  GENERAL_REGS, MAC_REGS, ALL_REGS, LIM_REG_CLASSES
};

#define N_REG_CLASSES ((int) LIM_REG_CLASSES)

/* Give names of register classes as strings for dump file.  */

#define REG_CLASS_NAMES \
{ "NO_REGS", "COUNTER_REGS", "SOURCE_REGS", "DESTINATION_REGS", \
  "GENERAL_REGS", "MAC_REGS", "ALL_REGS", "LIM_REGS" }

/* Define which registers fit in which classes.
   This is an initializer for a vector of HARD_REG_SET
   of length N_REG_CLASSES.  */

#define REG_CLASS_CONTENTS			\
{      {0},		/* No regs      */	\
   {0x010},		/* COUNTER_REGS */	\
   {0x020},		/* SOURCE_REGS */	\
   {0x040},		/* DESTINATION_REGS */	\
   {0xeff},		/* GENERAL_REGS */	\
   {0x100},		/* MAC_REGS */		\
   {0xfff},		/* ALL_REGS	*/	\
}

/* The same information, inverted:
   Return the class number of the smallest class containing
   reg number REGNO.  This could be a conditional expression
   or could index an array.  */

#define REGNO_REG_CLASS(REGNO)				\
  ((REGNO) == MAC_REG ? MAC_REGS			\
   : (REGNO) == COUNTER_REG ? COUNTER_REGS		\
   : (REGNO) == SOURCE_REG ? SOURCE_REGS		\
   : (REGNO) == DESTINATION_REG ? DESTINATION_REGS	\
   : GENERAL_REGS)

/* The class value for index registers, and the one for base regs.  */

#define INDEX_REG_CLASS (TARGET_H8300SX ? GENERAL_REGS : NO_REGS)
#define BASE_REG_CLASS  GENERAL_REGS

/* Get reg_class from a letter such as appears in the machine description.

   'a' is the MAC register.  */

#define REG_CLASS_FROM_LETTER(C) (h8300_reg_class_from_letter (C))

/* The letters I, J, K, L, M, N, O, P in a register constraint string
   can be used to stand for particular ranges of immediate operands.
   This macro defines what the ranges are.
   C is the letter, and VALUE is a constant value.
   Return 1 if VALUE is in the range specified by C.  */

#define CONST_OK_FOR_I(VALUE) ((VALUE) == 0)
#define CONST_OK_FOR_J(VALUE) (((VALUE) & 0xff) == 0)
#define CONST_OK_FOR_L(VALUE)				\