m68hc11.h

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#define SOFT_TMP_REGNUM          10

/* The soft-register which is used to save the Z register
   (see Z register replacement notes in m68hc11.c).  */
#define SOFT_Z_REGNUM            11

/* The soft-register which is used to save either X or Y.  */
#define SOFT_SAVED_XY_REGNUM     12

/* A fake clobber register for 68HC12 patterns.  */
#define FAKE_CLOBBER_REGNUM     (13)

/* Define 32 soft-registers of 16-bit each.  By default,
   only 12 of them are enabled and can be used by GCC.  The
   -msoft-reg-count=<n> option allows to control the number of valid
   soft-registers. GCC can put 32-bit values in them
   by allocating consecutive registers.  The first 3 soft-registers
   are never allocated by GCC.  They are used in case the insn template needs
   a temporary register, or for the Z register replacement.  */

#define MAX_SOFT_REG_COUNT      (32)
#define SOFT_REG_FIXED          0, 0, 0, 0, 0, 0, 0, 0, \
				0, 0, 0, 0, 1, 1, 1, 1, \
				1, 1, 1, 1, 1, 1, 1, 1, \
				1, 1, 1, 1, 1, 1, 1, 1
#define SOFT_REG_USED           0, 0, 0, 0, 0, 0, 0, 0, \
				0, 0, 0, 0, 1, 1, 1, 1, \
				1, 1, 1, 1, 1, 1, 1, 1, \
				1, 1, 1, 1, 1, 1, 1, 1
#define SOFT_REG_ORDER		\
SOFT_REG_FIRST, SOFT_REG_FIRST+1,SOFT_REG_FIRST+2,SOFT_REG_FIRST+3,\
SOFT_REG_FIRST+4, SOFT_REG_FIRST+5,SOFT_REG_FIRST+6,SOFT_REG_FIRST+7,\
SOFT_REG_FIRST+8, SOFT_REG_FIRST+9,SOFT_REG_FIRST+10,SOFT_REG_FIRST+11,\
SOFT_REG_FIRST+12, SOFT_REG_FIRST+13,SOFT_REG_FIRST+14,SOFT_REG_FIRST+15,\
SOFT_REG_FIRST+16, SOFT_REG_FIRST+17,SOFT_REG_FIRST+18,SOFT_REG_FIRST+19,\
SOFT_REG_FIRST+20, SOFT_REG_FIRST+21,SOFT_REG_FIRST+22,SOFT_REG_FIRST+23,\
SOFT_REG_FIRST+24, SOFT_REG_FIRST+25,SOFT_REG_FIRST+26,SOFT_REG_FIRST+27,\
SOFT_REG_FIRST+28, SOFT_REG_FIRST+29,SOFT_REG_FIRST+30,SOFT_REG_FIRST+31

#define SOFT_REG_NAMES							\
"*_.d1",  "*_.d2",  "*_.d3",  "*_.d4", \
"*_.d5",  "*_.d6",  "*_.d7",  "*_.d8",	\
"*_.d9",  "*_.d10", "*_.d11", "*_.d12", \
"*_.d13", "*_.d14", "*_.d15", "*_.d16",	\
"*_.d17", "*_.d18", "*_.d19", "*_.d20", \
"*_.d21", "*_.d22", "*_.d23", "*_.d24", \
"*_.d25", "*_.d26", "*_.d27", "*_.d28", \
"*_.d29", "*_.d30", "*_.d31", "*_.d32"

/* First available soft-register for GCC.  */
#define SOFT_REG_FIRST          (SOFT_SAVED_XY_REGNUM+2)

/* Last available soft-register for GCC.  */
#define SOFT_REG_LAST           (SOFT_REG_FIRST+MAX_SOFT_REG_COUNT)
#define SOFT_FP_REGNUM		(SOFT_REG_LAST)
#define SOFT_AP_REGNUM		(SOFT_FP_REGNUM+1)

/* Number of actual hardware registers. The hardware registers are assigned
   numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. 
   All registers that the compiler knows about must be given numbers, even
   those that are not normally considered general registers.  */
#define FIRST_PSEUDO_REGISTER	(SOFT_REG_LAST+2)

/* 1 for registers that have pervasive standard uses and are not available
   for the register allocator.  */
#define FIXED_REGISTERS \
  {0, 0, 0, 1, 1, 1, 1, 1,   0, 1,  1,   1,1, 1, SOFT_REG_FIXED, 1, 1}
/* X, D, Y, SP,PC,A, B, CCR, Z, FP,ZTMP,ZR,XYR, FK, D1 - D32, SOFT-FP, AP */

/* 1 for registers not available across function calls. For our pseudo
   registers, all are available.  */
#define CALL_USED_REGISTERS \
  {1, 1, 1, 1, 1, 1, 1, 1,   1, 1,  1,   1,1, 1, SOFT_REG_USED, 1, 1}
/* X, D, Y, SP,PC,A, B, CCR, Z, FP, ZTMP,ZR,XYR, D1 - 32,     SOFT-FP, AP */


/* Define this macro to change register usage conditional on target flags.

   The soft-registers are disabled or enabled according to the
  -msoft-reg-count=<n> option.  */


#define CONDITIONAL_REGISTER_USAGE (m68hc11_conditional_register_usage ())

/* List the order in which to allocate registers.  Each register must be
   listed once, even those in FIXED_REGISTERS.  */
#define REG_ALLOC_ORDER							\
{ HARD_D_REGNUM, HARD_X_REGNUM, HARD_Y_REGNUM,				\
  SOFT_REG_ORDER, HARD_Z_REGNUM, HARD_PC_REGNUM, HARD_A_REGNUM,		\
  HARD_B_REGNUM, HARD_CCR_REGNUM, HARD_FP_REGNUM, SOFT_FP_REGNUM,	\
  HARD_SP_REGNUM, SOFT_TMP_REGNUM, SOFT_Z_REGNUM, SOFT_SAVED_XY_REGNUM, \
  SOFT_AP_REGNUM, FAKE_CLOBBER_REGNUM  }

/* A C expression for the number of consecutive hard registers,
   starting at register number REGNO, required to hold a value of
   mode MODE.  */
#define HARD_REGNO_NREGS(REGNO, MODE) \
((Q_REGNO_P (REGNO)) ? (GET_MODE_SIZE (MODE)) : \
   ((GET_MODE_SIZE (MODE) + HARD_REG_SIZE - 1) / HARD_REG_SIZE))

/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
    - 8 bit values are stored anywhere (except the SP register).
    - 16 bit values can be stored in any register whose mode is 16
    - 32 bit values can be stored in D, X registers or in a soft register
      (except the last one because we need 2 soft registers)
    - Values whose size is > 32 bit are not stored in real hard
      registers.  They may be stored in soft registers if there are
      enough of them.  */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
     hard_regno_mode_ok (REGNO,MODE)

/* Value is 1 if it is a good idea to tie two pseudo registers when one has
   mode MODE1 and one has mode MODE2.  If HARD_REGNO_MODE_OK could produce
   different values for MODE1 and MODE2, for any hard reg, then this must be
   0 for correct output.

   All modes are tieable except QImode.  */
#define MODES_TIEABLE_P(MODE1, MODE2)                   \
     (((MODE1) == (MODE2))                              \
      || ((MODE1) != QImode && (MODE2) != QImode))


/* Define the classes of registers for register constraints in the
   machine description.  Also define ranges of constants.

   One of the classes must always be named ALL_REGS and include all hard regs.
   If there is more than one class, another class must be named NO_REGS
   and contain no registers.

   The name GENERAL_REGS must be the name of a class (or an alias for
   another name such as ALL_REGS).  This is the class of registers
   that is allowed by "g" or "r" in a register constraint.
   Also, registers outside this class are allocated only when
   instructions express preferences for them.

   The classes must be numbered in nondecreasing order; that is,
   a larger-numbered class must never be contained completely
   in a smaller-numbered class.

   For any two classes, it is very desirable that there be another
   class that represents their union.  */

/* The M68hc11 has so few registers that it's not possible for GCC to
   do any register allocation without breaking. We extend the processor
   registers by having soft registers. These registers are treated as
   hard registers by GCC but they are located in memory and accessed by page0
   accesses (IND mode).  */
enum reg_class
{
  NO_REGS,
  D_REGS,			/* 16-bit data register */
  X_REGS,			/* 16-bit X register */
  Y_REGS,			/* 16-bit Y register */
  SP_REGS,			/* 16 bit stack pointer */
  DA_REGS,			/* 8-bit A reg.  */
  DB_REGS,			/* 8-bit B reg.  */
  Z_REGS,			/* 16-bit fake Z register */
  D8_REGS,			/* 8-bit A or B reg.  */
  Q_REGS,			/* 8-bit (byte (QI)) data (A, B or D) */
  D_OR_X_REGS,			/* D or X register */
  D_OR_Y_REGS,			/* D or Y register */
  D_OR_SP_REGS,			/* D or SP register */
  X_OR_Y_REGS,			/* IX or Y register */
  A_REGS,			/* 16-bit address register (X, Y, Z) */
  X_OR_SP_REGS,			/* X or SP register */
  Y_OR_SP_REGS,			/* Y or SP register */
  X_OR_Y_OR_D_REGS,		/* X, Y or D */
  A_OR_D_REGS,			/* X, Y, Z or D */
  A_OR_SP_REGS,			/* X, Y, Z or SP */
  H_REGS,			/* 16-bit hard register (D, X, Y, Z, SP) */
  S_REGS,			/* 16-bit soft register */
  D_OR_S_REGS,			/* 16-bit soft register or D register */
  X_OR_S_REGS,			/* 16-bit soft register or X register */
  Y_OR_S_REGS,			/* 16-bit soft register or Y register */
  Z_OR_S_REGS,			/* 16-bit soft register or Z register */
  SP_OR_S_REGS,			/* 16-bit soft register or SP register */
  D_OR_X_OR_S_REGS,		/* 16-bit soft register or D or X register */
  D_OR_Y_OR_S_REGS,		/* 16-bit soft register or D or Y register */
  D_OR_SP_OR_S_REGS,		/* 16-bit soft register or D or SP register */
  A_OR_S_REGS,			/* 16-bit soft register or X, Y registers */
  D_OR_A_OR_S_REGS,		/* 16-bit soft register or D, X, Y registers */
  TMP_REGS,			/* 16 bit fake scratch register */
  D_OR_A_OR_TMP_REGS,		/* General scratch register */
  G_REGS,			/* 16-bit general register
                                   (H_REGS + soft registers) */
  ALL_REGS,
  LIM_REG_CLASSES
};

/* alias GENERAL_REGS to G_REGS.  */
#define GENERAL_REGS	G_REGS

#define N_REG_CLASSES	(int) LIM_REG_CLASSES

/* Give names of register classes as strings for dump file.  */
#define REG_CLASS_NAMES \
{ "NO_REGS",                                    \
      "D_REGS",                                 \
      "X_REGS",                                 \
      "Y_REGS",                                 \
      "SP_REGS",                                \
      "DA_REGS",                                \
      "DB_REGS",                                \
      "D8_REGS",                                \
      "Z_REGS",                                 \
      "Q_REGS",                                 \
      "D_OR_X_REGS",                            \
      "D_OR_Y_REGS",                            \
      "D_OR_SP_REGS",                           \
      "X_OR_Y_REGS",                            \
      "A_REGS",                                 \
      "X_OR_SP_REGS",                           \
      "Y_OR_SP_REGS",                           \
      "X_OR_Y_OR_D_REGS",                       \
      "A_OR_D_REGS",                            \
      "A_OR_SP_REGS",                           \
      "H_REGS",                                 \
      "S_REGS",                                 \
      "D_OR_S_REGS",                            \
      "X_OR_S_REGS",                            \
      "Y_OR_S_REGS",                            \
      "Z_OR_S_REGS",                            \
      "SP_OR_S_REGS",                           \
      "D_OR_X_OR_S_REGS",                       \
      "D_OR_Y_OR_S_REGS",                       \
      "D_OR_SP_OR_S_REGS",                      \
      "A_OR_S_REGS",                            \
      "D_OR_A_OR_S_REGS",                       \
      "TMP_REGS",				\
      "D_OR_A_OR_TMP_REGS",			\
      "G_REGS",                                 \
      "ALL_REGS" }

/* An initializer containing the contents of the register classes,
   as integers which are bit masks.  The Nth integer specifies the
   contents of class N.  The way the integer MASK is interpreted is
   that register R is in the class if `MASK & (1 << R)' is 1.  */

/*--------------------------------------------------------------
   X		0x00000001
   D		0x00000002
   Y		0x00000004
   SP		0x00000008
   PC		0x00000010
   A		0x00000020
   B		0x00000040
   CCR		0x00000080
   Z		0x00000100
   FRAME        0x00000200
   ZTMP		0x00000400
   ZREG		0x00000800
   XYREG	0x00001000
   FAKE         0x00002000
   Di		0xFFFFc000, 0x03FFF
   SFRAME       0x00000000, 0x04000
   AP           0x00000000, 0x08000

   D_OR_X_REGS represents D+X. It is used for 32-bits numbers.
   A_REGS      represents a valid base register for indexing. It represents
	       X,Y and the Z register.
   S_REGS      represents the soft-registers. This includes the hard frame
	       and soft frame registers.
--------------------------------------------------------------*/

#define REG_CLASS_CONTENTS \
/* NO_REGS */		{{ 0x00000000, 0x00000000 },			\
/* D_REGS  */		 { 0x00000002, 0x00000000 }, /* D */            \
/* X_REGS  */		 { 0x00000001, 0x00000000 }, /* X */            \
/* Y_REGS  */		 { 0x00000004, 0x00000000 }, /* Y */            \
/* SP_REGS */		 { 0x00000008, 0x00000000 }, /* SP */           \
/* DA_REGS */		 { 0x00000020, 0x00000000 }, /* A */            \
/* DB_REGS */		 { 0x00000040, 0x00000000 }, /* B */            \
/* Z_REGS  */		 { 0x00000100, 0x00000000 }, /* Z */            \
/* D8_REGS */		 { 0x00000060, 0x00000000 }, /* A B */          \
/* Q_REGS  */		 { 0x00000062, 0x00000000 }, /* A B D */        \
/* D_OR_X_REGS */        { 0x00000003, 0x00000000 }, /* D X */          \
/* D_OR_Y_REGS */        { 0x00000006, 0x00000000 }, /* D Y */          \
/* D_OR_SP_REGS */       { 0x0000000A, 0x00000000 }, /* D SP */         \
/* X_OR_Y_REGS  */	 { 0x00000005, 0x00000000 }, /* X Y */          \
/* A_REGS  */		 { 0x00000105, 0x00000000 }, /* X Y Z */        \
/* X_OR_SP_REGS */       { 0x00000009, 0x00000000 }, /* X SP */         \
/* Y_OR_SP_REGS */       { 0x0000000C, 0x00000000 }, /* Y SP */         \
/* X_OR_Y_OR_D_REGS */   { 0x00000007, 0x00000000 }, /* D X Y */        \
/* A_OR_D_REGS  */       { 0x00000107, 0x00000000 }, /* D X Y Z */      \
/* A_OR_SP_REGS */       { 0x0000010D, 0x00000000 }, /* X Y SP */       \
/* H_REGS  */		 { 0x0000010F, 0x00000000 }, /* D X Y SP */     \
/* S_REGS  */		 { 0xFFFFDE00, 0x00007FFF }, /* _.D,..,FP,Z*  */  \
/* D_OR_S_REGS */	 { 0xFFFFDE02, 0x00007FFF }, /* D _.D */        \
/* X_OR_S_REGS */	 { 0xFFFFDE01, 0x00007FFF }, /* X _.D */        \
/* Y_OR_S_REGS */	 { 0xFFFFDE04, 0x00007FFF }, /* Y _.D */        \
/* Z_OR_S_REGS */	 { 0xFFFFDF00, 0x00007FFF }, /* Z _.D */        \
/* SP_OR_S_REGS */	 { 0xFFFFDE08, 0x00007FFF }, /* SP _.D */	\
/* D_OR_X_OR_S_REGS */	 { 0xFFFFDE03, 0x00007FFF }, /* D X _.D */      \
/* D_OR_Y_OR_S_REGS */	 { 0xFFFFDE06, 0x00007FFF }, /* D Y _.D */      \
/* D_OR_SP_OR_S_REGS */	 { 0xFFFFDE0A, 0x00007FFF }, /* D SP _.D */     \
/* A_OR_S_REGS */	 { 0xFFFFDF05, 0x00007FFF }, /* X Y _.D */      \
/* D_OR_A_OR_S_REGS */	 { 0xFFFFDF07, 0x00007FFF }, /* D X Y _.D */    \
/* TMP_REGS  */	         { 0x00002000, 0x00000000 }, /* FAKE */		\
/* D_OR_A_OR_TMP_REGS*/  { 0x00002107, 0x00000000 }, /* D X Y Z Fake */  \
/* G_REGS  */		 { 0xFFFFFF1F, 0x00007FFF }, /* ? _.D D X Y */   \
/* ALL_REGS*/		 { 0xFFFFFFFF, 0x00007FFF }}


/* set up a C expression whose value is a register class containing hard
   register REGNO */
#define Q_REGNO_P(REGNO)	((REGNO) == HARD_A_REGNUM \
				 || (REGNO) == HARD_B_REGNUM)
#define Q_REG_P(X)              (REG_P (X) && Q_REGNO_P (REGNO (X)))

#define D_REGNO_P(REGNO)        ((REGNO) == HARD_D_REGNUM)