rs6000.md

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  "TARGET_POWER || TARGET_ISEL"
  "
{
  if (TARGET_ISEL)
    {
      rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
      DONE;
    }
  operands[3] = gen_reg_rtx (SImode);
  operands[4] = gen_reg_rtx (SImode);
  operands[5] = GEN_INT (-2147483647 - 1);
}")

(define_expand "umaxsi3"
  [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
			      (match_dup 5)))
   (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
			      (match_dup 5)))
   (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
				       (const_int 0)
				       (minus:SI (match_dup 4) (match_dup 3))))
   (set (match_operand:SI 0 "gpc_reg_operand" "")
	(plus:SI (match_dup 3) (match_dup 1)))]
  "TARGET_POWER || TARGET_ISEL"
  "
{
  if (TARGET_ISEL)
    {
      rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
      DONE;
    }
  operands[3] = gen_reg_rtx (SImode);
  operands[4] = gen_reg_rtx (SImode);
  operands[5] = GEN_INT (-2147483647 - 1);
}")

(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
			     (match_operand:SI 2 "reg_or_short_operand" "rI"))
			 (const_int 0)
			 (minus:SI (match_dup 2) (match_dup 1))))]
  "TARGET_POWER"
  "doz%I2 %0,%1,%2")

(define_insn ""
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
	(compare:CC
	 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
			      (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
			  (const_int 0)
			  (minus:SI (match_dup 2) (match_dup 1)))
	 (const_int 0)))
   (clobber (match_scratch:SI 3 "=r,r"))]
  "TARGET_POWER"
  "@
   doz%I2. %3,%1,%2
   #"
  [(set_attr "type" "delayed_compare")
   (set_attr "length" "4,8")])

(define_split
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
	(compare:CC
	 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
			      (match_operand:SI 2 "reg_or_short_operand" ""))
			  (const_int 0)
			  (minus:SI (match_dup 2) (match_dup 1)))
	 (const_int 0)))
   (clobber (match_scratch:SI 3 ""))]
  "TARGET_POWER && reload_completed"
  [(set (match_dup 3)
	(if_then_else:SI (gt (match_dup 1) (match_dup 2))
			  (const_int 0)
			  (minus:SI (match_dup 2) (match_dup 1))))
   (set (match_dup 0)
	(compare:CC (match_dup 3)
		    (const_int 0)))]
  "")

(define_insn ""
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
	(compare:CC
	 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
			      (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
			  (const_int 0)
			  (minus:SI (match_dup 2) (match_dup 1)))
	 (const_int 0)))
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
	(if_then_else:SI (gt (match_dup 1) (match_dup 2))
			 (const_int 0)
			 (minus:SI (match_dup 2) (match_dup 1))))]
  "TARGET_POWER"
  "@
   doz%I2. %0,%1,%2
   #"
  [(set_attr "type" "delayed_compare")
   (set_attr "length" "4,8")])

(define_split
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
	(compare:CC
	 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
			      (match_operand:SI 2 "reg_or_short_operand" ""))
			  (const_int 0)
			  (minus:SI (match_dup 2) (match_dup 1)))
	 (const_int 0)))
   (set (match_operand:SI 0 "gpc_reg_operand" "")
	(if_then_else:SI (gt (match_dup 1) (match_dup 2))
			 (const_int 0)
			 (minus:SI (match_dup 2) (match_dup 1))))]
  "TARGET_POWER && reload_completed"
  [(set (match_dup 0)
	(if_then_else:SI (gt (match_dup 1) (match_dup 2))
			 (const_int 0)
			 (minus:SI (match_dup 2) (match_dup 1))))
   (set (match_dup 3)
	(compare:CC (match_dup 0)
		    (const_int 0)))]
  "")

;; We don't need abs with condition code because such comparisons should
;; never be done.
(define_expand "abssi2"
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
	(abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
  ""
  "
{
  if (TARGET_ISEL)
    {
      emit_insn (gen_abssi2_isel (operands[0], operands[1]));
      DONE;
    }
  else if (! TARGET_POWER)
    {
      emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
      DONE;
    }
}")

(define_insn "*abssi2_power"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
  "TARGET_POWER"
  "abs %0,%1")

(define_insn_and_split "abssi2_isel"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
        (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
   (clobber (match_scratch:SI 2 "=&b"))
   (clobber (match_scratch:CC 3 "=y"))]
  "TARGET_ISEL"
  "#"
  "&& reload_completed"
  [(set (match_dup 2) (neg:SI (match_dup 1)))
   (set (match_dup 3)
	(compare:CC (match_dup 1)
		    (const_int 0)))
   (set (match_dup 0)
	(if_then_else:SI (ge (match_dup 3)
			     (const_int 0))
			 (match_dup 1)
			 (match_dup 2)))]
  "")

(define_insn_and_split "abssi2_nopower"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
        (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
   (clobber (match_scratch:SI 2 "=&r,&r"))]
  "! TARGET_POWER && ! TARGET_ISEL"
  "#"
  "&& reload_completed"
  [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
   (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
   (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
  "")

(define_insn "*nabs_power"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
  "TARGET_POWER"
  "nabs %0,%1")

(define_insn_and_split "*nabs_nopower"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
        (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
   (clobber (match_scratch:SI 2 "=&r,&r"))]
  "! TARGET_POWER"
  "#"
  "&& reload_completed"
  [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
   (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
   (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
  "")

(define_expand "neg<mode>2"
  [(set (match_operand:SDI 0 "gpc_reg_operand" "")
	(neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
  ""
  "")

(define_insn "*neg<mode>2_internal"
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
	(neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
  ""
  "neg %0,%1")

(define_insn ""
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
	(compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
		    (const_int 0)))
   (clobber (match_scratch:P 2 "=r,r"))]
  ""
  "@
   neg. %2,%1
   #"
  [(set_attr "type" "fast_compare")
   (set_attr "length" "4,8")])

(define_split
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
	(compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
		    (const_int 0)))
   (clobber (match_scratch:P 2 ""))]
  "reload_completed"
  [(set (match_dup 2)
	(neg:P (match_dup 1)))
   (set (match_dup 0)
	(compare:CC (match_dup 2)
		    (const_int 0)))]
  "")

(define_insn ""
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
	(compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
		    (const_int 0)))
   (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
	(neg:P (match_dup 1)))]
  ""
  "@
   neg. %0,%1
   #"
  [(set_attr "type" "fast_compare")
   (set_attr "length" "4,8")])

(define_split
  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
	(compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
		    (const_int 0)))
   (set (match_operand:P 0 "gpc_reg_operand" "")
	(neg:P (match_dup 1)))]
  "reload_completed"
  [(set (match_dup 0)
	(neg:P (match_dup 1)))
   (set (match_dup 2)
	(compare:CC (match_dup 0)
		    (const_int 0)))]
  "")

(define_insn "clz<mode>2"
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
	(clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
  ""
  "{cntlz|cntlz<wd>} %0,%1")

(define_expand "ctz<mode>2"
  [(set (match_dup 2)
	(neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
   (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
					  (match_dup 2)))
	      (clobber (scratch:CC))])
   (set (match_dup 4) (clz:GPR (match_dup 3)))
   (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
	(minus:GPR (match_dup 5) (match_dup 4)))]
  ""
  {
     operands[2] = gen_reg_rtx (<MODE>mode);
     operands[3] = gen_reg_rtx (<MODE>mode);
     operands[4] = gen_reg_rtx (<MODE>mode);
     operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
  })

(define_expand "ffs<mode>2"
  [(set (match_dup 2)
	(neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
   (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
					  (match_dup 2)))
	      (clobber (scratch:CC))])
   (set (match_dup 4) (clz:GPR (match_dup 3)))
   (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
	(minus:GPR (match_dup 5) (match_dup 4)))]
  ""
  {
     operands[2] = gen_reg_rtx (<MODE>mode);
     operands[3] = gen_reg_rtx (<MODE>mode);
     operands[4] = gen_reg_rtx (<MODE>mode);
     operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
  })

(define_expand "popcount<mode>2"
  [(set (match_dup 2)
	(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
		     UNSPEC_POPCNTB))
   (set (match_dup 3)
	(mult:GPR (match_dup 2) (match_dup 4)))
   (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
	(lshiftrt:GPR (match_dup 3) (match_dup 5)))]
  "TARGET_POPCNTB"
  {
    operands[2] = gen_reg_rtx (<MODE>mode);
    operands[3] = gen_reg_rtx (<MODE>mode);
    operands[4] = force_reg (<MODE>mode,
			     <MODE>mode == SImode
			     ? GEN_INT (0x01010101)
			     : GEN_INT ((HOST_WIDE_INT)
					0x01010101 << 32 | 0x01010101));
    operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 8);
  })

(define_insn "popcntb<mode>2"
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
        (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
                     UNSPEC_POPCNTB))]
  "TARGET_POPCNTB"
  "popcntb %0,%1")

(define_expand "mulsi3"
  [(use (match_operand:SI 0 "gpc_reg_operand" ""))
   (use (match_operand:SI 1 "gpc_reg_operand" ""))
   (use (match_operand:SI 2 "reg_or_short_operand" ""))]
  ""
  "
{
  if (TARGET_POWER)
    emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
  else
    emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
  DONE;
}")

(define_insn "mulsi3_mq"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
	(mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
		 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
   (clobber (match_scratch:SI 3 "=q,q"))]
  "TARGET_POWER"
  "@
   {muls|mullw} %0,%1,%2
   {muli|mulli} %0,%1,%2"
   [(set (attr "type")
      (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
		(const_string "imul3")
             (match_operand:SI 2 "short_cint_operand" "")
		(const_string "imul2")]
	(const_string "imul")))])

(define_insn "mulsi3_no_mq"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
	(mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
		 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
  "! TARGET_POWER"
  "@
   {muls|mullw} %0,%1,%2
   {muli|mulli} %0,%1,%2"
   [(set (attr "type")
      (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
		(const_string "imul3")
             (match_operand:SI 2 "short_cint_operand" "")
		(const_string "imul2")]
	(const_string "imul")))])

(define_insn "*mulsi3_mq_internal1"
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
			     (match_operand:SI 2 "gpc_reg_operand" "r,r"))
		    (const_int 0)))
   (clobber (match_scratch:SI 3 "=r,r"))
   (clobber (match_scratch:SI 4 "=q,q"))]
  "TARGET_POWER"
  "@
   {muls.|mullw.} %3,%1,%2
   #"
  [(set_attr "type" "imul_compare")
   (set_attr "length" "4,8")])

(define_split
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
			     (match_operand:SI 2 "gpc_reg_operand" ""))
		    (const_int 0)))
   (clobber (match_scratch:SI 3 ""))
   (clobber (match_scratch:SI 4 ""))]
  "TARGET_POWER && reload_completed"
  [(parallel [(set (match_dup 3)
	(mult:SI (match_dup 1) (match_dup 2)))
   (clobber (match_dup 4))])
   (set (match_dup 0)
	(compare:CC (match_dup 3)
		    (const_int 0)))]
  "")

(define_insn "*mulsi3_no_mq_internal1"
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
			     (match_operand:SI 2 "gpc_reg_operand" "r,r"))
		    (const_int 0)))
   (clobber (match_scratch:SI 3 "=r,r"))]
  "! TARGET_POWER"
  "@
   {muls.|mullw.} %3,%1,%2
   #"
  [(set_attr "type" "imul_compare")
   (set_attr "length" "4,8")])

(define_split
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
			     (match_operand:SI 2 "gpc_reg_operand" ""))
		    (const_int 0)))
   (clobber (match_scratch:SI 3 ""))]
  "! TARGET_POWER && reload_completed"
  [(set (match_dup 3)
	(mult:SI (match_dup 1) (match_dup 2)))
   (set (match_dup 0)
	(compare:CC (match_dup 3)
		    (const_int 0)))]
  "")

(define_insn "*mulsi3_mq_internal2"
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
			     (match_operand:SI 2 "gpc_reg_operand" "r,r"))
		    (const_int 0)))
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")