mt.md

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  mt_compare_op0 = operands[0];
  mt_compare_op1 = operands[1];
  DONE;
}")


;; Branches

(define_expand "beq"
  [(use (match_operand 0 "" ""))]
  ""
  "
{
  mt_emit_cbranch (EQ, operands[0], mt_compare_op0, mt_compare_op1);
  DONE;
}")

(define_expand "bne"
  [(use (match_operand 0 "" ""))]
  ""
  "
{
  mt_emit_cbranch (NE, operands[0], mt_compare_op0, mt_compare_op1);
  DONE;
}")

(define_expand "bge"
  [(use (match_operand 0 "" ""))]
  ""
  "
{
  mt_emit_cbranch (GE, operands[0], mt_compare_op0, mt_compare_op1);
  DONE;
}")

(define_expand "bgt"
  [(use (match_operand 0 "" ""))]
  ""
  "
{
  mt_emit_cbranch (GT, operands[0], mt_compare_op0, mt_compare_op1);
  DONE;
}")

(define_expand "ble"
  [(use (match_operand 0 "" ""))]
  ""
  "
{
  mt_emit_cbranch (LE, operands[0], mt_compare_op0, mt_compare_op1);
  DONE;
}")

(define_expand "blt"
  [(use (match_operand 0 "" ""))]
  ""
  "
{
  mt_emit_cbranch (LT, operands[0], mt_compare_op0, mt_compare_op1);
  DONE;
}")

(define_expand "bgeu"
  [(use (match_operand 0 "" ""))]
  ""
  "
{
  mt_emit_cbranch (GEU, operands[0], mt_compare_op0, mt_compare_op1);
  DONE;
}")

(define_expand "bgtu"
  [(use (match_operand 0 "" ""))]
  ""
  "
{
  mt_emit_cbranch (GTU, operands[0], mt_compare_op0, mt_compare_op1);
  DONE;
}")

(define_expand "bleu"
  [(use (match_operand 0 "" ""))]
  ""
  "
{
  mt_emit_cbranch (LEU, operands[0], mt_compare_op0, mt_compare_op1);
  DONE;
}")

(define_expand "bltu"
  [(use (match_operand 0 "" ""))]
  ""
  "
{
  mt_emit_cbranch (LTU, operands[0], mt_compare_op0, mt_compare_op1);
  DONE;
}")

(define_expand "bunge"
  [(use (match_operand 0 "" ""))]
  ""
  "
{
  mt_emit_cbranch (GEU, operands[0], mt_compare_op0, mt_compare_op1);
  DONE;
}")

(define_expand "bungt"
  [(use (match_operand 0 "" ""))]
  ""
  "
{
  mt_emit_cbranch (GTU, operands[0], mt_compare_op0, mt_compare_op1);
  DONE;
}")

(define_expand "bunle"
  [(use (match_operand 0 "" ""))]
  ""
  "
{
  mt_emit_cbranch (LEU, operands[0], mt_compare_op0, mt_compare_op1);
  DONE;
}")

(define_expand "bunlt"
  [(use (match_operand 0 "" ""))]
  ""
  "
{
  mt_emit_cbranch (LTU, operands[0], mt_compare_op0, mt_compare_op1);
  DONE;
}")

(define_insn "*beq_true"
  [(set (pc)
	(if_then_else (eq (match_operand:SI 0 "reg_or_0_operand" "rJ")
			  (match_operand:SI 1 "reg_or_0_operand" "rJ"))
		      (label_ref (match_operand 2 "" ""))
		      (pc)))]
  ""
  "breq %z0, %z1, %l2%#"
  [(set_attr "length" "4")
   (set_attr "type" "branch")])

(define_insn "*beq_false"
  [(set (pc)
	(if_then_else (eq (match_operand:SI 0 "reg_or_0_operand" "rJ")
			  (match_operand:SI 1 "reg_or_0_operand" "rJ"))
		      (pc)
		      (label_ref (match_operand 2 "" ""))))]
  ""
  "brne %z0, %z1, %l2%#"
  [(set_attr "length" "4")
   (set_attr "type" "branch")])


(define_insn "*bne_true"
  [(set (pc)
	(if_then_else (ne (match_operand:SI 0 "reg_or_0_operand" "rJ")
			  (match_operand:SI 1 "reg_or_0_operand" "rJ"))
		      (label_ref (match_operand 2 "" ""))
		      (pc)))]
  ""
  "brne %z0, %z1, %l2%#"
  [(set_attr "length" "4")
   (set_attr "type" "branch")])

(define_insn "*bne_false"
  [(set (pc)
	(if_then_else (ne (match_operand:SI 0 "reg_or_0_operand" "rJ")
			  (match_operand:SI 1 "reg_or_0_operand" "rJ"))
		      (pc)
		      (label_ref (match_operand 2 "" ""))))]
  ""
  "breq %z0, %z1, %l2%#"
  [(set_attr "length" "4")
   (set_attr "type" "branch")])

(define_insn "*blt_true"
  [(set (pc)
	(if_then_else (lt (match_operand:SI 0 "reg_or_0_operand" "rJ")
			  (match_operand:SI 1 "reg_or_0_operand" "rJ"))
		      (label_ref (match_operand 2 "" ""))
		      (pc)))]
  ""
  "brlt %z0, %z1, %l2%#"
  [(set_attr "length" "4")
   (set_attr "type" "branch")])

(define_insn "*blt_false"
  [(set (pc)
	(if_then_else (lt (match_operand:SI 0 "reg_or_0_operand" "rJ")
			  (match_operand:SI 1 "reg_or_0_operand" "rJ"))
		      (pc)
		      (label_ref (match_operand 2 "" ""))))]
  ""
  "brle %z1, %z0,%l2%#"
  [(set_attr "length" "4")
   (set_attr "type" "branch")])

(define_insn "*ble_true"
  [(set (pc)
	(if_then_else (le (match_operand:SI 0 "reg_or_0_operand" "rJ")
			  (match_operand:SI 1 "reg_or_0_operand" "rJ"))
		      (label_ref (match_operand 2 "" ""))
		      (pc)))]
  ""
  "brle %z0, %z1, %l2%#"
  [(set_attr "length" "4")
   (set_attr "type" "branch")])

(define_insn "*ble_false"
  [(set (pc)
	(if_then_else (le (match_operand:SI 0 "reg_or_0_operand" "rJ")
			  (match_operand:SI 1 "reg_or_0_operand" "rJ"))
		      (pc)
		      (label_ref (match_operand 2 "" ""))))]
  ""
  "brlt %z1, %z0,%l2%#"
  [(set_attr "length" "4")
   (set_attr "type" "branch")])

(define_insn "*bgt_true"
  [(set (pc)
	(if_then_else (gt (match_operand:SI 0 "reg_or_0_operand" "rJ")
			  (match_operand:SI 1 "reg_or_0_operand" "rJ"))
		      (label_ref (match_operand 2 "" ""))
		      (pc)))]
  ""
  "brlt %z1, %z0, %l2%#"
  [(set_attr "length" "4")
   (set_attr "type" "branch")])

(define_insn "*bgt_false"
  [(set (pc)
	(if_then_else (gt (match_operand:SI 0 "reg_or_0_operand" "rJ")
			  (match_operand:SI 1 "reg_or_0_operand" "rJ"))
		      (pc)
		      (label_ref (match_operand 2 "" ""))))]
  ""
  "brle %z0, %z1, %l2%#"
  [(set_attr "length" "4")
   (set_attr "type" "branch")])

(define_insn "*bge_true"
  [(set (pc)
	(if_then_else (ge (match_operand:SI 0 "reg_or_0_operand" "rJ")
			  (match_operand:SI 1 "reg_or_0_operand" "rJ"))
		      (label_ref (match_operand 2 "" ""))
		      (pc)))]
  ""
  "brle %z1, %z0,%l2%#"
  [(set_attr "length" "4")
   (set_attr "type" "branch")])

(define_insn "*bge_false"
  [(set (pc)
	(if_then_else (ge (match_operand:SI 0 "reg_or_0_operand" "rJ")
			  (match_operand:SI 1 "reg_or_0_operand" "rJ"))
		      (pc)
		      (label_ref (match_operand 2 "" ""))))]
  ""
  "brlt %z0, %z1, %l2%#"
  [(set_attr "length" "4")
   (set_attr "type" "branch")])

;; No unsigned operators on Morpho mt.  All the unsigned operations are
;; converted to the signed operations above.


;; Set flag operations

;; "seq", "sne", "slt", "sle", "sgt", "sge", "sltu", "sleu",
;; "sgtu", and "sgeu" don't exist as regular instruction on the
;; mt, so these are not defined

;; Call and branch instructions

(define_expand "call"
  [(parallel [(call (mem:SI (match_operand:SI 0 "register_operand" ""))
			    (match_operand 1 "" ""))
	      (clobber (reg:SI 14))])]
  ""
  "
{
    operands[0] = force_reg (SImode, XEXP (operands[0], 0));
}")

(define_insn "call_internal"
  [(call (mem:SI (match_operand 0 "register_operand" "r"))
	 (match_operand 1 "" ""))
   ;; possibly add a clobber of the reg that gets the return address
   (clobber (reg:SI 14))]
  ""
  "jal r14, %0%#"
  [(set_attr "length" "4")
   (set_attr "type" "call")])

(define_expand "call_value"
  [(parallel [(set (match_operand 0 "register_operand" "")
		   (call (mem:SI (match_operand:SI 1 "register_operand" ""))
				 (match_operand 2 "general_operand" "")))
	      (clobber (reg:SI 14))])]
  ""
  "
{
    operands[1] = force_reg (SImode, XEXP (operands[1], 0));
}")


(define_insn "call_value_internal"
  [(set (match_operand 0 "register_operand" "=r")
	(call (mem:SI (match_operand 1 "register_operand" "r"))
	      (match_operand 2 "" "")))
	;; possibly add a clobber of the reg that gets the return address
	(clobber (reg:SI 14))]
  ""
  "jal r14, %1%#"
  [(set_attr "length" "4")
   (set_attr "type" "call")])

;; Subroutine return
(define_insn "return_internal"
  [(const_int 2)
   (return)
   (use (reg:SI 14))]
  ""
  "jal r0, r14%#"
  [(set_attr "length" "4")
   (set_attr "type" "call")])

;; Interrupt return
(define_insn "return_interrupt_internal"
  [(const_int 3)
   (return)
   (use (reg:SI 15))]
  ""
  "reti r15%#"
  [(set_attr "length" "4")
   (set_attr "type" "call")])

;; Subroutine return
(define_insn "eh_return_internal"
  [(return)
   (use (reg:SI 7))
   (use (reg:SI 8))
   (use (reg:SI 11))
   (use (reg:SI 10))]
  ""
  "jal r0, r11%#"
  [(set_attr "length" "4")
   (set_attr "type" "call")])


;; Normal unconditional jump
(define_insn "jump"
  [(set (pc) (label_ref (match_operand 0 "" "")))]
  ""
  "jmp %l0%#"
  [(set_attr "length" "4")
   (set_attr "type" "branch")])

;; Indirect jump through a register
(define_insn "indirect_jump"
  [(set (pc) (match_operand 0 "register_operand" "r"))]
  ""
  "jal r0,%0%#"
  [(set_attr "length" "4")
   (set_attr "type" "call")])

(define_insn "tablejump"
  [(set (pc) (match_operand:SI 0 "register_operand" "r"))
   (use (label_ref (match_operand 1 "" "")))]
  ""
  "jal r0, %0%#"
  [(set_attr "length" "4")
   (set_attr "type" "call")])


(define_expand "prologue"
  [(const_int 1)]
  ""
  "
{
  mt_expand_prologue ();
  DONE;
}")

(define_expand "epilogue"
  [(const_int 2)]
  ""
  "
{
  mt_expand_epilogue (NORMAL_EPILOGUE);
  DONE;
}")


(define_expand "eh_return"
  [(use (match_operand:SI 0 "register_operand" "r"))]
  ""
  "
{
  mt_expand_eh_return (operands);
  DONE;
}")


(define_insn_and_split "eh_epilogue"
  [(unspec [(match_operand 0 "register_operand" "r")] 6)]
  ""
  "#"
  "reload_completed"
  [(const_int 1)]
  "mt_emit_eh_epilogue (operands); DONE;"
)

;; No operation, needed in case the user uses -g but not -O.
(define_insn "nop"
  [(const_int 0)]
  ""
  "nop"
  [(set_attr "length" "4")
   (set_attr "type" "arith")])

;; ::::::::::::::::::::
;; ::
;; :: UNSPEC_VOLATILE usage
;; ::
;; ::::::::::::::::::::
;; 
;;	0	blockage
;;	1	Enable interrupts
;;	2	Disable interrupts
;;

;; Pseudo instruction that prevents the scheduler from moving code above this
;; point.
(define_insn "blockage"
  [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
  ""
  ""
  [(set_attr "length" "0")])

;; Trap instruction to allow usage of the __builtin_trap function
(define_insn "trap"
  [(trap_if (const_int 1) (const_int 0))
   (clobber (reg:SI 14))]
  ""
  "si	r14%#"
  [(set_attr "length" "4")
   (set_attr "type" "branch")])

(define_expand "conditional_trap"
  [(trap_if (match_operator 0 "comparison_operator"
			    [(match_dup 2)
			     (match_dup 3)])
	    (match_operand 1 "const_int_operand" ""))]
  ""
  "
{
  operands[2] = mt_compare_op0;
  operands[3] = mt_compare_op1;
}")

;; Templates to control handling of interrupts

;; Enable interrupts template
(define_insn "ei"
  [(unspec_volatile [(const_int 0)] UNSPEC_EI)]
  ""
  "ei"
  [(set_attr "length" "4")])

;; Enable interrupts template
(define_insn "di"
  [(unspec_volatile [(const_int 0)] UNSPEC_DI)]
  ""
  "di"
  [(set_attr "length" "4")])