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📄 predicates.md

📁 linux下编程用 编译软件
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      && GET_CODE (op) == PLUS      && REG_P (XEXP (op, 0))      && REG_P (XEXP (op, 1)))    return 0;  return memory_address_p (mode, op);});; Accept REG and any CONST_INT that can be moved in one instruction;; into a general register.(define_predicate "reg_or_cint_move_operand"  (match_code "subreg,reg,const_int"){  if (register_operand (op, mode))    return 1;  return (GET_CODE (op) == CONST_INT && cint_ok_for_move (INTVAL (op)));});; TODO: Add a comment here.(define_predicate "pic_label_operand"  (match_code "label_ref,const"){  if (!flag_pic)    return 0;  switch (GET_CODE (op))    {    case LABEL_REF:      return 1;    case CONST:      op = XEXP (op, 0);      return (GET_CODE (XEXP (op, 0)) == LABEL_REF	      && GET_CODE (XEXP (op, 1)) == CONST_INT);    default:      return 0;    }});; TODO: Add a comment here.(define_predicate "fp_reg_operand"  (match_code "reg"){  return reg_renumber && FP_REG_P (op);});; Return truth value of whether OP can be used as an operand in a;; three operand arithmetic insn that accepts registers of mode MODE;; or 14-bit signed integers.(define_predicate "arith_operand"  (match_code "subreg,reg,const_int"){  return (register_operand (op, mode)	  || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));});; Return truth value of whether OP can be used as an operand in a;; three operand arithmetic insn that accepts registers of mode MODE;; or 11-bit signed integers.(define_predicate "arith11_operand"  (match_code "subreg,reg,const_int"){  return (register_operand (op, mode)	  || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));});; A constant integer suitable for use in a PRE_MODIFY memory;; reference.(define_predicate "pre_cint_operand"  (match_code "const_int"){  return (GET_CODE (op) == CONST_INT	  && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);});; A constant integer suitable for use in a POST_MODIFY memory;; reference.(define_predicate "post_cint_operand"  (match_code "const_int"){  return (GET_CODE (op) == CONST_INT	  && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);});; TODO: Add a comment here.(define_predicate "arith_double_operand"  (match_code "subreg,reg,const_double"){  return (register_operand (op, mode)	  || (GET_CODE (op) == CONST_DOUBLE	      && GET_MODE (op) == mode	      && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))	      && ((CONST_DOUBLE_HIGH (op) >= 0)		  == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));});; Return truth value of whether OP is an integer which fits the range;; constraining immediate operands in three-address insns, or is an;; integer register.(define_predicate "ireg_or_int5_operand"  (match_code "const_int,reg"){  return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))	  || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));});; Return truth value of whether OP is an integer which fits the range;; constraining immediate operands in three-address insns.(define_predicate "int5_operand"  (match_code "const_int"){  return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));});; Return truth value of whether OP is an integer which fits the range;; constraining immediate operands in three-address insns.(define_predicate "uint5_operand"  (match_code "const_int"){  return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));});; Return truth value of whether OP is an integer which fits the range;; constraining immediate operands in three-address insns.(define_predicate "int11_operand"  (match_code "const_int"){  return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));});; Return truth value of whether OP is an integer which fits the range;; constraining immediate operands in three-address insns.(define_predicate "uint32_operand"  (match_code "const_int,const_double"){#if HOST_BITS_PER_WIDE_INT > 32  /* All allowed constants will fit a CONST_INT.  */  return (GET_CODE (op) == CONST_INT	  && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));#else  return (GET_CODE (op) == CONST_INT	  || (GET_CODE (op) == CONST_DOUBLE	      && CONST_DOUBLE_HIGH (op) == 0));#endif});; Return truth value of whether OP is an integer which fits the range;; constraining immediate operands in three-address insns.(define_predicate "arith5_operand"  (match_code "subreg,reg,const_int"){  return register_operand (op, mode) || int5_operand (op, mode);});; True iff depi or extru can be used to compute (reg & OP).(define_predicate "and_operand"  (match_code "subreg,reg,const_int"){  return (register_operand (op, mode)	  || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));});; True iff depi can be used to compute (reg | OP).(define_predicate "ior_operand"  (match_code "const_int"){  return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));});; True iff OP is a CONST_INT of the forms 0...0xxxx or;; 0...01...1xxxx. Such values can be the left hand side x in (x <<;; r), using the zvdepi instruction.(define_predicate "lhs_lshift_cint_operand"  (match_code "const_int"){  unsigned HOST_WIDE_INT x;  if (GET_CODE (op) != CONST_INT)    return 0;  x = INTVAL (op) >> 4;  return (x & (x + 1)) == 0;});; TODO: Add a comment here.(define_predicate "lhs_lshift_operand"  (match_code "subreg,reg,const_int"){  return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);});; TODO: Add a comment here.(define_predicate "arith32_operand"  (match_code "subreg,reg,const_int"){  return register_operand (op, mode) || GET_CODE (op) == CONST_INT;});; TODO: Add a comment here.(define_predicate "pc_or_label_operand"  (match_code "pc,label_ref"){  return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);});; TODO: Add a comment here.(define_predicate "plus_xor_ior_operator"  (match_code "plus,xor,ior"){  return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR	  || GET_CODE (op) == IOR);});; Return 1 if OP is a CONST_INT with the value 2, 4, or 8.  These are;; the valid constant for shadd instructions.(define_predicate "shadd_operand"  (match_code "const_int"){  return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));});; TODO: Add a comment here.(define_predicate "div_operand"  (match_code "reg,const_int"){  return (mode == SImode	  && ((GET_CODE (op) == REG && REGNO (op) == 25)	      || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0		  && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));});; Return nonzero if OP is an integer register, else return zero.(define_predicate "ireg_operand"  (match_code "reg"){  return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);});; Return 1 if this is a comparison operator.  This allows the use of;; MATCH_OPERATOR to recognize all the branch insns.(define_predicate "cmpib_comparison_operator"  (match_code "eq,ne,lt,le,leu,gt,gtu,ge"){  return ((mode == VOIDmode || GET_MODE (op) == mode)          && (GET_CODE (op) == EQ	      || GET_CODE (op) == NE	      || GET_CODE (op) == GT	      || GET_CODE (op) == GTU	      || GET_CODE (op) == GE	      || GET_CODE (op) == LT	      || GET_CODE (op) == LE	      || GET_CODE (op) == LEU));});; Return 1 if OP is an operator suitable for use in a movb;; instruction.(define_predicate "movb_comparison_operator"  (match_code "eq,ne,lt,ge"){  return (GET_CODE (op) == EQ || GET_CODE (op) == NE	  || GET_CODE (op) == LT || GET_CODE (op) == GE);})

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