pa.h

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		      force_reg (Pmode, plus_constant ((TRAMP), 32)));	\
      tmp = memory_address (Pmode, plus_constant ((TRAMP), 24));	\
      emit_move_insn (gen_rtx_MEM (Pmode, tmp),				\
		      gen_rtx_REG (Pmode, 27));				\
									\
      /* fdc and fic only use registers for the address to flush,	\
	 they do not accept integer displacements.  We align the	\
	 start and end addresses to the beginning of their respective	\
	 cache lines to minimize the number of lines flushed.  */	\
      tmp = force_reg (Pmode, plus_constant ((TRAMP), 32));		\
      emit_insn (gen_anddi3 (start_addr, tmp,				\
			     GEN_INT (-MIN_CACHELINE_SIZE)));		\
      tmp = force_reg (Pmode,						\
		       plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1));	\
      emit_insn (gen_anddi3 (end_addr, tmp,				\
			     GEN_INT (-MIN_CACHELINE_SIZE)));		\
      emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE));	\
      emit_insn (gen_dcacheflush (start_addr, end_addr, line_length));	\
      emit_insn (gen_icacheflush (start_addr, end_addr, line_length,	\
				  gen_reg_rtx (Pmode),			\
				  gen_reg_rtx (Pmode)));		\
    }									\
}

/* Perform any machine-specific adjustment in the address of the trampoline.
   ADDR contains the address that was passed to INITIALIZE_TRAMPOLINE.
   Adjust the trampoline address to point to the plabel at offset 44.  */
   
#define TRAMPOLINE_ADJUST_ADDRESS(ADDR) \
  if (!TARGET_64BIT) (ADDR) = memory_address (Pmode, plus_constant ((ADDR), 46))

/* Implement `va_start' for varargs and stdarg.  */

#define EXPAND_BUILTIN_VA_START(valist, nextarg) \
  hppa_va_start (valist, nextarg)

/* Addressing modes, and classification of registers for them. 

   Using autoincrement addressing modes on PA8000 class machines is
   not profitable.  */

#define HAVE_POST_INCREMENT (pa_cpu < PROCESSOR_8000)
#define HAVE_POST_DECREMENT (pa_cpu < PROCESSOR_8000)

#define HAVE_PRE_DECREMENT (pa_cpu < PROCESSOR_8000)
#define HAVE_PRE_INCREMENT (pa_cpu < PROCESSOR_8000)

/* Macros to check register numbers against specific register classes.  */

/* The following macros assume that X is a hard or pseudo reg number.
   They give nonzero only if X is a hard reg of the suitable class
   or a pseudo reg currently allocated to a suitable hard reg.
   Since they use reg_renumber, they are safe only once reg_renumber
   has been allocated, which happens in local-alloc.c.  */

#define REGNO_OK_FOR_INDEX_P(X) \
  ((X) && ((X) < 32							\
   || (X >= FIRST_PSEUDO_REGISTER					\
       && reg_renumber							\
       && (unsigned) reg_renumber[X] < 32)))
#define REGNO_OK_FOR_BASE_P(X) \
  ((X) && ((X) < 32							\
   || (X >= FIRST_PSEUDO_REGISTER					\
       && reg_renumber							\
       && (unsigned) reg_renumber[X] < 32)))
#define REGNO_OK_FOR_FP_P(X) \
  (FP_REGNO_P (X)							\
   || (X >= FIRST_PSEUDO_REGISTER					\
       && reg_renumber							\
       && FP_REGNO_P (reg_renumber[X])))

/* Now macros that check whether X is a register and also,
   strictly, whether it is in a specified class.

   These macros are specific to the HP-PA, and may be used only
   in code for printing assembler insns and in conditions for
   define_optimization.  */

/* 1 if X is an fp register.  */

#define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))

/* Maximum number of registers that can appear in a valid memory address.  */

#define MAX_REGS_PER_ADDRESS 2

/* Non-TLS symbolic references.  */
#define PA_SYMBOL_REF_TLS_P(RTX) \
  (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)

/* Recognize any constant value that is a valid address except
   for symbolic addresses.  We get better CSE by rejecting them
   here and allowing hppa_legitimize_address to break them up.  We
   use most of the constants accepted by CONSTANT_P, except CONST_DOUBLE.  */

#define CONSTANT_ADDRESS_P(X) \
  ((GET_CODE (X) == LABEL_REF 						\
   || (GET_CODE (X) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (X))		\
   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
   || GET_CODE (X) == HIGH) 						\
   && (reload_in_progress || reload_completed || ! symbolic_expression_p (X)))

/* A C expression that is nonzero if we are using the new HP assembler.  */

#ifndef NEW_HP_ASSEMBLER
#define NEW_HP_ASSEMBLER 0
#endif

/* The macros below define the immediate range for CONST_INTS on
   the 64-bit port.  Constants in this range can be loaded in three
   instructions using a ldil/ldo/depdi sequence.  Constants outside
   this range are forced to the constant pool prior to reload.  */

#define MAX_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) 32 << 31)
#define MIN_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) -32 << 31)
#define LEGITIMATE_64BIT_CONST_INT_P(X) \
  ((X) >= MIN_LEGIT_64BIT_CONST_INT && (X) < MAX_LEGIT_64BIT_CONST_INT)

/* A C expression that is nonzero if X is a legitimate constant for an
   immediate operand.

   We include all constant integers and constant doubles, but not
   floating-point, except for floating-point zero.  We reject LABEL_REFs
   if we're not using gas or the new HP assembler. 

   In 64-bit mode, we reject CONST_DOUBLES.  We also reject CONST_INTS
   that need more than three instructions to load prior to reload.  This
   limit is somewhat arbitrary.  It takes three instructions to load a
   CONST_INT from memory but two are memory accesses.  It may be better
   to increase the allowed range for CONST_INTS.  We may also be able
   to handle CONST_DOUBLES.  */

#define LEGITIMATE_CONSTANT_P(X)				\
  ((GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT			\
    || (X) == CONST0_RTX (GET_MODE (X)))			\
   && (NEW_HP_ASSEMBLER || TARGET_GAS || GET_CODE (X) != LABEL_REF)	\
   && !(TARGET_64BIT && GET_CODE (X) == CONST_DOUBLE)		\
   && !(TARGET_64BIT && GET_CODE (X) == CONST_INT		\
	&& !(HOST_BITS_PER_WIDE_INT <= 32			\
	     || (reload_in_progress || reload_completed)	\
	     || LEGITIMATE_64BIT_CONST_INT_P (INTVAL (X))	\
	     || cint_ok_for_move (INTVAL (X))))			\
   && !function_label_operand (X, VOIDmode))

/* Target flags set on a symbol_ref.  */

/* Set by ASM_OUTPUT_SYMBOL_REF when a symbol_ref is output.  */
#define SYMBOL_FLAG_REFERENCED (1 << SYMBOL_FLAG_MACH_DEP_SHIFT)
#define SYMBOL_REF_REFERENCED_P(RTX) \
  ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_REFERENCED) != 0)

/* Subroutines for EXTRA_CONSTRAINT.

   Return 1 iff OP is a pseudo which did not get a hard register and
   we are running the reload pass.  */
#define IS_RELOADING_PSEUDO_P(OP) \
  ((reload_in_progress					\
    && GET_CODE (OP) == REG				\
    && REGNO (OP) >= FIRST_PSEUDO_REGISTER		\
    && reg_renumber [REGNO (OP)] < 0))

/* Return 1 iff OP is a scaled or unscaled index address.  */
#define IS_INDEX_ADDR_P(OP) \
  (GET_CODE (OP) == PLUS				\
   && GET_MODE (OP) == Pmode				\
   && (GET_CODE (XEXP (OP, 0)) == MULT			\
       || GET_CODE (XEXP (OP, 1)) == MULT		\
       || (REG_P (XEXP (OP, 0))				\
	   && REG_P (XEXP (OP, 1)))))

/* Return 1 iff OP is a LO_SUM DLT address.  */
#define IS_LO_SUM_DLT_ADDR_P(OP) \
  (GET_CODE (OP) == LO_SUM				\
   && GET_MODE (OP) == Pmode				\
   && REG_P (XEXP (OP, 0))				\
   && REG_OK_FOR_BASE_P (XEXP (OP, 0))			\
   && GET_CODE (XEXP (OP, 1)) == UNSPEC)

/* Optional extra constraints for this machine. Borrowed from sparc.h.

   `A' is a LO_SUM DLT memory operand.

   `Q' is any memory operand that isn't a symbolic, indexed or lo_sum
       memory operand.  Note that an unassigned pseudo register is such a
       memory operand.  Needed because reload will generate these things
       and then not re-recognize the insn, causing constrain_operands to
       fail.

   `R' is a scaled/unscaled indexed memory operand.

   `S' is the constant 31.

   `T' is for floating-point loads and stores.

   `U' is the constant 63.

   `W' is a register indirect memory operand.  We could allow short
       displacements but GO_IF_LEGITIMATE_ADDRESS can't tell when a
       long displacement is valid.  This is only used for prefetch
       instructions with the `sl' completer.  */

#define EXTRA_CONSTRAINT(OP, C) \
  ((C) == 'Q' ?								\
   (IS_RELOADING_PSEUDO_P (OP)						\
    || (GET_CODE (OP) == MEM						\
	&& (reload_in_progress						\
	    || memory_address_p (GET_MODE (OP), XEXP (OP, 0)))		\
	&& !symbolic_memory_operand (OP, VOIDmode)			\
	&& !IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0))				\
	&& !IS_INDEX_ADDR_P (XEXP (OP, 0))))				\
   : ((C) == 'W' ?							\
      (GET_CODE (OP) == MEM						\
       && REG_P (XEXP (OP, 0))						\
       && REG_OK_FOR_BASE_P (XEXP (OP, 0)))				\
   : ((C) == 'A' ?							\
      (GET_CODE (OP) == MEM						\
       && IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0)))				\
   : ((C) == 'R' ?							\
      (GET_CODE (OP) == MEM						\
       && IS_INDEX_ADDR_P (XEXP (OP, 0)))				\
   : ((C) == 'T' ? 							\
      (GET_CODE (OP) == MEM						\
       && !IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0))				\
       && !IS_INDEX_ADDR_P (XEXP (OP, 0))				\
       /* Floating-point loads and stores are used to load		\
	  integer values as well as floating-point values.		\
	  They don't have the same set of REG+D address modes		\
	  as integer loads and stores.  PA 1.x supports only		\
	  short displacements.  PA 2.0 supports long displacements	\
	  but the base register needs to be aligned.			\
									\
	  The checks in GO_IF_LEGITIMATE_ADDRESS for SFmode and		\
	  DFmode test the validity of an address for use in a		\
	  floating point load or store.  So, we use SFmode/DFmode	\
	  to see if the address is valid for a floating-point		\
	  load/store operation.  */					\
       && memory_address_p ((GET_MODE_SIZE (GET_MODE (OP)) == 4		\
			     ? SFmode					\
			     : DFmode),					\
			    XEXP (OP, 0)))				\
   : ((C) == 'S' ?							\
      (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 31)			\
   : ((C) == 'U' ?							\
      (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 63) : 0)))))))
	

/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
   and check its validity for a certain class.
   We have two alternate definitions for each of them.
   The usual definition accepts all pseudo regs; the other rejects
   them unless they have been allocated suitable hard regs.
   The symbol REG_OK_STRICT causes the latter definition to be used.

   Most source files want to accept pseudo regs in the hope that
   they will get allocated to the class that the insn wants them to be in.
   Source files for reload pass need to be strict.
   After reload, it makes no difference, since pseudo regs have
   been eliminated by then.  */

#ifndef REG_OK_STRICT

/* Nonzero if X is a hard reg that can be used as an index
   or if it is a pseudo reg.  */
#define REG_OK_FOR_INDEX_P(X) \
(REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
/* Nonzero if X is a hard reg that can be used as a base reg
   or if it is a pseudo reg.  */
#define REG_OK_FOR_BASE_P(X) \
(REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))

#else

/* Nonzero if X is a hard reg that can be used as an index.  */
#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
/* Nonzero if X is a hard reg that can be used as a base reg.  */
#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))

#endif

/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
   valid memory address for an instruction.  The MODE argument is the
   machine mode for the MEM expression that wants to use this address.

   On HP PA-RISC, the legitimate address forms are REG+SMALLINT,
   REG+REG, and REG+(REG*SCALE).  The indexed address forms are only
   available with floating point loads and stores, and integer loads.
   We get better code by allowing indexed addresses in the initial
   RTL generation.

   The acceptance of indexed addresses as legitimate implies that we
   must provide patterns for doing indexed integer stores, or the move
   expanders must force the address of an indexed store to a register.
   We have adopted the latter approach.
   
   Another function of GO_IF_LEGITIMATE_ADDRESS is to ensure that
   the base register is a valid pointer for indexed instructions.
   On targets that have non-equivalent space registers, we have to
   know at the time of assembler output which register in a REG+REG
   pair is the base register.  The REG_POINTER flag is sometimes lost
   in reload and the following passes, so it can't be relied on during
   code generation.  Thus, we either have to canonicalize the order
   of the registers in REG+REG indexed addresses, or treat REG+REG
   addresses separately and provide patterns for both permutations.

   The latter approach requires several hundred additional lines of
   code in pa.md.  The downside to canonicalizing is that a PLUS
   in the wrong order can't combine to form to make a scaled indexed
   memory operand.  As we won't need to canonicalize the operands if
   the REG_POINTER lossage can be fixed, it seems better canonicalize.

   We initially break out scaled indexed addresses in canonical order
   in emit_move_sequence.  LEGITIMIZE_ADDRESS also canonicalizes
   scaled indexed addresses during RTL generation.  However, fold_rtx
   has its own opinion on how the operands of a PLUS should be ordered.
   If one of the operands is equivalent to a constant, it will make
   that operand the second operand.  As the base register is likely to
   be equivalent to a SYMBOL_REF, we have made it the second operand.

   GO_IF_LEGITIMATE_ADDRESS accepts REG+REG as legitimate when the
   operands are in the order INDEX+BASE on targets with non-equivalent
   space registers, and in any order on targets with equivalent space
   registers.  It accepts both MULT+BASE and BASE+MULT for scaled indexing.

   We treat a SYMBOL_REF as legitimate if it is part of the current
   function's constant-pool, because such addresses can actually be
   output as REG+SMALLINT. 

   Note we only allow 5 bit immediates for access to a constant address;
   doing so avoids losing for loading/storing a FP register at an address
   which will not fit in 5 bits.  */

#define VAL_5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x10 < 0x20)