arm.h

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/* For the Thumb the high registers cannot be used as base registers
   when addressing quantities in QI or HI mode; if we don't know the
   mode, then we must be conservative.  */
#define MODE_BASE_REG_CLASS(MODE)					\
    (TARGET_ARM ? GENERAL_REGS :					\
     (((MODE) == SImode) ? BASE_REGS : LO_REGS))

/* For Thumb we can not support SP+reg addressing, so we return LO_REGS
   instead of BASE_REGS.  */
#define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS

/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
   registers explicitly used in the rtl to be used as spill registers
   but prevents the compiler from extending the lifetime of these
   registers.  */
#define SMALL_REGISTER_CLASSES   TARGET_THUMB

/* Get reg_class from a letter such as appears in the machine description.
   We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
   ARM, but several more letters for the Thumb.  */
#define REG_CLASS_FROM_LETTER(C)  	\
  (  (C) == 'f' ? FPA_REGS		\
   : (C) == 'v' ? CIRRUS_REGS		\
   : (C) == 'w' ? VFP_REGS		\
   : (C) == 'y' ? IWMMXT_REGS		\
   : (C) == 'z' ? IWMMXT_GR_REGS	\
   : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS)	\
   : TARGET_ARM ? NO_REGS		\
   : (C) == 'h' ? HI_REGS		\
   : (C) == 'b' ? BASE_REGS		\
   : (C) == 'k' ? STACK_REG		\
   : (C) == 'c' ? CC_REG		\
   : NO_REGS)

/* The letters I, J, K, L and M in a register constraint string
   can be used to stand for particular ranges of immediate operands.
   This macro defines what the ranges are.
   C is the letter, and VALUE is a constant value.
   Return 1 if VALUE is in the range specified by C.
	I: immediate arithmetic operand (i.e. 8 bits shifted as required).
	J: valid indexing constants.
	K: ~value ok in rhs argument of data operand.
	L: -value ok in rhs argument of data operand.
        M: 0..32, or a power of 2  (for shifts, or mult done by shift).  */
#define CONST_OK_FOR_ARM_LETTER(VALUE, C)  		\
  ((C) == 'I' ? const_ok_for_arm (VALUE) :		\
   (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) :	\
   (C) == 'K' ? (const_ok_for_arm (~(VALUE))) :		\
   (C) == 'L' ? (const_ok_for_arm (-(VALUE))) :		\
   (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32))		\
		 || (((VALUE) & ((VALUE) - 1)) == 0))	\
   : 0)

#define CONST_OK_FOR_THUMB_LETTER(VAL, C)		\
  ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 :	\
   (C) == 'J' ? (VAL) > -256 && (VAL) < 0 :		\
   (C) == 'K' ? thumb_shiftable_const (VAL) :		\
   (C) == 'L' ? (VAL) > -8 && (VAL) < 8	:		\
   (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024	\
		   && ((VAL) & 3) == 0) :		\
   (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) :	\
   (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508)		\
   : 0)

#define CONST_OK_FOR_LETTER_P(VALUE, C)					\
  (TARGET_ARM ?								\
   CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))

/* Constant letter 'G' for the FP immediate constants.
   'H' means the same constant negated.  */
#define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C)			\
    ((C) == 'G' ? arm_const_double_rtx (X) :			\
     (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)

#define CONST_DOUBLE_OK_FOR_LETTER_P(X, C)			\
  (TARGET_ARM ?							\
   CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)

/* For the ARM, `Q' means that this is a memory operand that is just
   an offset from a register.
   `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
   address.  This means that the symbol is in the text segment and can be
   accessed without using a load.
   'D' Prefixes a number of const_double operands where:
   'Da' is a constant that takes two ARM insns to load.
   'Db' takes three ARM insns.
   'Dc' takes four ARM insns, if we allow that in this compilation.
   'U' Prefixes an extended memory constraint where:
   'Uv' is an address valid for VFP load/store insns.
   'Uy' is an address valid for iwmmxt load/store insns.
   'Uq' is an address valid for ldrsb.  */

#define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR)				\
  (((C) == 'D') ? ((GET_CODE (OP) == CONST_DOUBLE			\
		    || GET_CODE (OP) == CONST_INT			\
		    || GET_CODE (OP) == CONST_VECTOR)			\
		   && (((STR)[1] == 'a'					\
			&& arm_const_double_inline_cost (OP) == 2)	\
		       || ((STR)[1] == 'b'				\
			   && arm_const_double_inline_cost (OP) == 3)	\
		       || ((STR)[1] == 'c'				\
			   && arm_const_double_inline_cost (OP) == 4	\
			   && !(optimize_size || arm_ld_sched)))) :	\
   ((C) == 'Q') ? (GET_CODE (OP) == MEM					\
		 && GET_CODE (XEXP (OP, 0)) == REG) :			\
   ((C) == 'R') ? (GET_CODE (OP) == MEM					\
		   && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF		\
		   && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) :		\
   ((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) :		\
   ((C) == 'T') ? cirrus_memory_offset (OP) :				\
   ((C) == 'U' && (STR)[1] == 'v') ? arm_coproc_mem_operand (OP, FALSE) : \
   ((C) == 'U' && (STR)[1] == 'y') ? arm_coproc_mem_operand (OP, TRUE) : \
   ((C) == 'U' && (STR)[1] == 'q')					\
    ? arm_extendqisi_mem_op (OP, GET_MODE (OP))				\
   : 0)

#define CONSTRAINT_LEN(C,STR)				\
  (((C) == 'U' || (C) == 'D') ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))

#define EXTRA_CONSTRAINT_THUMB(X, C)					\
  ((C) == 'Q' ? (GET_CODE (X) == MEM					\
		 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)

#define EXTRA_CONSTRAINT_STR(X, C, STR)		\
  (TARGET_ARM					\
   ? EXTRA_CONSTRAINT_STR_ARM (X, C, STR)	\
   : EXTRA_CONSTRAINT_THUMB (X, C))

#define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'U')

/* Given an rtx X being reloaded into a reg required to be
   in class CLASS, return the class of reg to actually use.
   In general this is just CLASS, but for the Thumb we prefer
   a LO_REGS class or a subset.  */
#define PREFERRED_RELOAD_CLASS(X, CLASS)	\
  (TARGET_ARM ? (CLASS) :			\
   ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))

/* Must leave BASE_REGS reloads alone */
#define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X)		\
  ((CLASS) != LO_REGS && (CLASS) != BASE_REGS				\
   ? ((true_regnum (X) == -1 ? LO_REGS					\
       : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS	\
       : NO_REGS)) 							\
   : NO_REGS)

#define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X)		\
  ((CLASS) != LO_REGS && (CLASS) != BASE_REGS				\
   ? ((true_regnum (X) == -1 ? LO_REGS					\
       : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS	\
       : NO_REGS)) 							\
   : NO_REGS)

/* Return the register class of a scratch register needed to copy IN into
   or out of a register in CLASS in MODE.  If it can be done directly,
   NO_REGS is returned.  */
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X)		\
  /* Restrict which direct reloads are allowed for VFP regs.  */ \
  ((TARGET_VFP && TARGET_HARD_FLOAT				\
    && (CLASS) == VFP_REGS)					\
   ? vfp_secondary_reload_class (MODE, X)			\
   : TARGET_ARM							\
   ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
    ? GENERAL_REGS : NO_REGS)					\
   : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))

/* If we need to load shorts byte-at-a-time, then we need a scratch.  */
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X)		\
  /* Restrict which direct reloads are allowed for VFP regs.  */ \
  ((TARGET_VFP && TARGET_HARD_FLOAT				\
    && (CLASS) == VFP_REGS)					\
    ? vfp_secondary_reload_class (MODE, X) :			\
  /* Cannot load constants into Cirrus registers.  */		\
   (TARGET_MAVERICK && TARGET_HARD_FLOAT			\
     && (CLASS) == CIRRUS_REGS					\
     && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF))		\
    ? GENERAL_REGS :						\
  (TARGET_ARM ?							\
   (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS)	\
      && CONSTANT_P (X))					\
   ? GENERAL_REGS :						\
   (((MODE) == HImode && ! arm_arch4				\
     && (GET_CODE (X) == MEM					\
	 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG)	\
	     && true_regnum (X) == -1)))			\
    ? GENERAL_REGS : NO_REGS)					\
   : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))

/* Try a machine-dependent way of reloading an illegitimate address
   operand.  If we find one, push the reload and jump to WIN.  This
   macro is used in only one place: `find_reloads_address' in reload.c.

   For the ARM, we wish to handle large displacements off a base
   register by splitting the addend across a MOV and the mem insn.
   This can cut the number of reloads needed.  */
#define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN)	   \
  do									   \
    {									   \
      if (GET_CODE (X) == PLUS						   \
	  && GET_CODE (XEXP (X, 0)) == REG				   \
	  && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER		   \
	  && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE)			   \
	  && GET_CODE (XEXP (X, 1)) == CONST_INT)			   \
	{								   \
	  HOST_WIDE_INT val = INTVAL (XEXP (X, 1));			   \
	  HOST_WIDE_INT low, high;					   \
									   \
	  if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT))	   \
	    low = ((val & 0xf) ^ 0x8) - 0x8;				   \
	  else if (TARGET_MAVERICK && TARGET_HARD_FLOAT)		   \
	    /* Need to be careful, -256 is not a valid offset.  */	   \
	    low = val >= 0 ? (val & 0xff) : -((-val) & 0xff);		   \
	  else if (MODE == SImode					   \
		   || (MODE == SFmode && TARGET_SOFT_FLOAT)		   \
		   || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
	    /* Need to be careful, -4096 is not a valid offset.  */	   \
	    low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff);		   \
	  else if ((MODE == HImode || MODE == QImode) && arm_arch4)	   \
	    /* Need to be careful, -256 is not a valid offset.  */	   \
	    low = val >= 0 ? (val & 0xff) : -((-val) & 0xff);		   \
	  else if (GET_MODE_CLASS (MODE) == MODE_FLOAT			   \
		   && TARGET_HARD_FLOAT && TARGET_FPA)			   \
	    /* Need to be careful, -1024 is not a valid offset.  */	   \
	    low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff);		   \
	  else								   \
	    break;							   \
									   \
	  high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff)	   \
		   ^ (unsigned HOST_WIDE_INT) 0x80000000)		   \
		  - (unsigned HOST_WIDE_INT) 0x80000000);		   \
	  /* Check for overflow or zero */				   \
	  if (low == 0 || high == 0 || (high + low != val))		   \
	    break;							   \
									   \
	  /* Reload the high part into a base reg; leave the low part	   \
	     in the mem.  */						   \
	  X = gen_rtx_PLUS (GET_MODE (X),				   \
			    gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0),	   \
					  GEN_INT (high)),		   \
			    GEN_INT (low));				   \
	  push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL,	   \
		       MODE_BASE_REG_CLASS (MODE), GET_MODE (X), 	   \
		       VOIDmode, 0, 0, OPNUM, TYPE);			   \
	  goto WIN;							   \
	}								   \
    }									   \
  while (0)

/* XXX If an HImode FP+large_offset address is converted to an HImode
   SP+large_offset address, then reload won't know how to fix it.  It sees
   only that SP isn't valid for HImode, and so reloads the SP into an index
   register, but the resulting address is still invalid because the offset
   is too big.  We fix it here instead by reloading the entire address.  */
/* We could probably achieve better results by defining PROMOTE_MODE to help
   cope with the variances between the Thumb's signed and unsigned byte and
   halfword load instructions.  */
#define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN)     \
do {									      \
  rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
  if (new_x)								      \
    {									      \
      X = new_x;							      \
      goto WIN;								      \
    }									      \
} while (0)

#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)   \
  if (TARGET_ARM)							   \
    ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
  else									   \
    THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)

/* Return the maximum number of consecutive registers
   needed to represent mode MODE in a register of class CLASS.
   ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
#define CLASS_MAX_NREGS(CLASS, MODE)  \
  (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))

/* If defined, gives a class of registers that cannot be used as the
   operand of a SUBREG that changes the mode of the object illegally.  */

/* Moves between FPA_REGS and GENERAL_REGS are two memory insns.  */
#define REGISTER_MOVE_COST(MODE, FROM, TO)		\
  (TARGET_ARM ?						\
   ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 :	\
    (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 :	\
    (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 :  \
    (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 :  \
    (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 :  \
    (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 :  \
    (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 :  \
    (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 :	\
    (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 :	\
   2)							\
   :							\
   ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)

/* Stack layout; function entry, exit and calling.  */

/* Define this if pushing a word on the stack
   makes the stack pointer a smaller address.  */
#define STACK_GROWS_DOWNWARD  1

/* Define this to nonzero if the nominal address of the stack frame
   is at the high-address end of the local variables;
   that is, each additional local variable allocated
   goes at a more negative offset in the frame.  */
#define FRAME_GROWS_DOWNWARD 1

/* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
   When present, it is one word in size, and sits at the top of the frame,
   between the soft frame pointer and either r7 or r11.

   We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
   and only then if some outgoing arguments are passed on the stack.  It would
   be tempting to also check whether the stack arguments are passed by indirect
   calls, but there seems to be no reason in principle why a post-reload pass
   couldn't convert a direct call into an indirect one.  */
#define CALLER_INTERWORKING_SLOT_SIZE			\
  (TARGET_CALLER_INTERWORKING				\
   && current_function_outgoing_args_size != 0		\
   ? UNITS_PER_WORD : 0)

/* Offset within stack frame to start allocating local variables at.
   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
   first local allocated.  Otherwise, it is the offset to the BEGINNING
   of the first local allocated.  */
#define STARTING_FRAME_OFFSET  0

/* If we generate an insn to push BYTES bytes,
   this says how many the stack pointer really advances by.  */
/* The push insns do not do this rounding implicitly.
   So don't define this.  */
/* #define PUSH_ROUNDING(NPUSHED)  ROUND_UP_WORD (NPUSHED) */

/* Define this if the maximum size of all the outgoing args is to be
   accumulated and pushed during the prologue.  The amount can be
   found in the variable current_function_outgoing_args_size.  */
#define ACCUMULATE_OUTGOING_ARGS 1

/* Offset of first parameter from the argument pointer register value.  */
#define FIRST_PARM_OFFSET(FNDECL)  (TARGET_ARM ? 4 : 0)

/* Value is the number of byte of arguments automatically
   popped when returning from a subroutine call.
   FUNDECL is the declaration node of the function (as a tree),
   FUNTYPE is the data type of the function (as a tree),