vax.c

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	/* PARALLELs whose first element sets the PC are aob,
	   sob insns.  They do change the cc's.  */
	CC_STATUS_INIT;
    }
  else
    CC_STATUS_INIT;
  if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
      && cc_status.value2
      && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
    cc_status.value2 = 0;
  if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM
      && cc_status.value2
      && GET_CODE (cc_status.value2) == MEM)
    cc_status.value2 = 0;
  /* Actual condition, one line up, should be that value2's address
     depends on value1, but that is too much of a pain.  */
}

/* Output integer move instructions.  */

const char *
vax_output_int_move (rtx insn ATTRIBUTE_UNUSED, rtx *operands,
		     enum machine_mode mode)
{
  switch (mode)
    {
    case SImode:
      if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
	{
	  if (push_operand (operands[0], SImode))
	    return "pushab %a1";
	  return "movab %a1,%0";
	}
      if (operands[1] == const0_rtx)
	return "clrl %0";
      if (GET_CODE (operands[1]) == CONST_INT
	  && (unsigned) INTVAL (operands[1]) >= 64)
	{
	  int i = INTVAL (operands[1]);
	  if ((unsigned)(~i) < 64)
	    return "mcoml %N1,%0";
	  if ((unsigned)i < 0x100)
	    return "movzbl %1,%0";
	  if (i >= -0x80 && i < 0)
	    return "cvtbl %1,%0";
	  if ((unsigned)i < 0x10000)
	    return "movzwl %1,%0";
	  if (i >= -0x8000 && i < 0)
	    return "cvtwl %1,%0";
	}
      if (push_operand (operands[0], SImode))
	return "pushl %1";
      return "movl %1,%0";

    case HImode:
      if (GET_CODE (operands[1]) == CONST_INT)
	{
	  int i = INTVAL (operands[1]);
	  if (i == 0)
	    return "clrw %0";
	  else if ((unsigned int)i < 64)
	    return "movw %1,%0";
	  else if ((unsigned int)~i < 64)
	    return "mcomw %H1,%0";
	  else if ((unsigned int)i < 256)
	    return "movzbw %1,%0";
	}
      return "movw %1,%0";

    case QImode:
      if (GET_CODE (operands[1]) == CONST_INT)
	{
	  int i = INTVAL (operands[1]);
	  if (i == 0)
	    return "clrb %0";
	  else if ((unsigned int)~i < 64)
	    return "mcomb %B1,%0";
	}
      return "movb %1,%0";

    default:
      gcc_unreachable ();
    }
}

/* Output integer add instructions.

   The space-time-opcode tradeoffs for addition vary by model of VAX.

   On a VAX 3 "movab (r1)[r2],r3" is faster than "addl3 r1,r2,r3",
   but it not faster on other models.

   "movab #(r1),r2" is usually shorter than "addl3 #,r1,r2", and is
   faster on a VAX 3, but some VAXen (e.g. VAX 9000) will stall if
   a register is used in an address too soon after it is set.
   Compromise by using movab only when it is shorter than the add
   or the base register in the address is one of sp, ap, and fp,
   which are not modified very often.  */

const char *
vax_output_int_add (rtx insn ATTRIBUTE_UNUSED, rtx *operands,
		    enum machine_mode mode)
{
  switch (mode)
    {
    case SImode:
      if (rtx_equal_p (operands[0], operands[1]))
	{
	  if (operands[2] == const1_rtx)
	    return "incl %0";
	  if (operands[2] == constm1_rtx)
	    return "decl %0";
	  if (GET_CODE (operands[2]) == CONST_INT
	      && (unsigned) (- INTVAL (operands[2])) < 64)
	    return "subl2 $%n2,%0";
	  if (GET_CODE (operands[2]) == CONST_INT
	      && (unsigned) INTVAL (operands[2]) >= 64
	      && GET_CODE (operands[1]) == REG
	      && ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768)
		   || REGNO (operands[1]) > 11))
	    return "movab %c2(%1),%0";
	  return "addl2 %2,%0";
	}

      if (rtx_equal_p (operands[0], operands[2]))
	return "addl2 %1,%0";

      if (GET_CODE (operands[2]) == CONST_INT
	  && INTVAL (operands[2]) < 32767
	  && INTVAL (operands[2]) > -32768
	  && GET_CODE (operands[1]) == REG
	  && push_operand (operands[0], SImode))
	return "pushab %c2(%1)";

      if (GET_CODE (operands[2]) == CONST_INT
	  && (unsigned) (- INTVAL (operands[2])) < 64)
	return "subl3 $%n2,%1,%0";

      if (GET_CODE (operands[2]) == CONST_INT
	  && (unsigned) INTVAL (operands[2]) >= 64
	  && GET_CODE (operands[1]) == REG
	  && ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768)
	       || REGNO (operands[1]) > 11))
	return "movab %c2(%1),%0";

      /* Add this if using gcc on a VAX 3xxx:
      if (REG_P (operands[1]) && REG_P (operands[2]))
	return "movab (%1)[%2],%0";
      */
      return "addl3 %1,%2,%0";

    case HImode:
      if (rtx_equal_p (operands[0], operands[1]))
	{
	  if (operands[2] == const1_rtx)
	    return "incw %0";
	  if (operands[2] == constm1_rtx)
	    return "decw %0";
	  if (GET_CODE (operands[2]) == CONST_INT
	      && (unsigned) (- INTVAL (operands[2])) < 64)
	    return "subw2 $%n2,%0";
	  return "addw2 %2,%0";
	}
      if (rtx_equal_p (operands[0], operands[2]))
	return "addw2 %1,%0";
      if (GET_CODE (operands[2]) == CONST_INT
	  && (unsigned) (- INTVAL (operands[2])) < 64)
	return "subw3 $%n2,%1,%0";
      return "addw3 %1,%2,%0";

    case QImode:
      if (rtx_equal_p (operands[0], operands[1]))
	{
	  if (operands[2] == const1_rtx)
	    return "incb %0";
	  if (operands[2] == constm1_rtx)
	    return "decb %0";
	  if (GET_CODE (operands[2]) == CONST_INT
	      && (unsigned) (- INTVAL (operands[2])) < 64)
	    return "subb2 $%n2,%0";
	  return "addb2 %2,%0";
	}
      if (rtx_equal_p (operands[0], operands[2]))
	return "addb2 %1,%0";
      if (GET_CODE (operands[2]) == CONST_INT
	  && (unsigned) (- INTVAL (operands[2])) < 64)
	return "subb3 $%n2,%1,%0";
      return "addb3 %1,%2,%0";

    default:
      gcc_unreachable ();
    }
}

/* Output a conditional branch.  */
const char *
vax_output_conditional_branch (enum rtx_code code)
{
  switch (code)
    {
      case EQ:  return "jeql %l0";
      case NE:  return "jneq %l0";
      case GT:  return "jgtr %l0";
      case LT:  return "jlss %l0";
      case GTU: return "jgtru %l0";
      case LTU: return "jlssu %l0";
      case GE:  return "jgeq %l0";
      case LE:  return "jleq %l0";
      case GEU: return "jgequ %l0";
      case LEU: return "jlequ %l0";
      default:
        gcc_unreachable ();
    }
}

/* 1 if X is an rtx for a constant that is a valid address.  */

int
legitimate_constant_address_p (rtx x)
{
  return (GET_CODE (x) == LABEL_REF || GET_CODE (x) == SYMBOL_REF
	  || GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST
	  || GET_CODE (x) == HIGH);
}

/* Nonzero if the constant value X is a legitimate general operand.
   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */

int
legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
{
  return 1;
}

/* The other macros defined here are used only in legitimate_address_p ().  */

/* Nonzero if X is a hard reg that can be used as an index
   or, if not strict, if it is a pseudo reg.  */
#define	INDEX_REGISTER_P(X, STRICT) \
(GET_CODE (X) == REG && (!(STRICT) || REGNO_OK_FOR_INDEX_P (REGNO (X))))

/* Nonzero if X is a hard reg that can be used as a base reg
   or, if not strict, if it is a pseudo reg.  */
#define	BASE_REGISTER_P(X, STRICT) \
(GET_CODE (X) == REG && (!(STRICT) || REGNO_OK_FOR_BASE_P (REGNO (X))))

#ifdef NO_EXTERNAL_INDIRECT_ADDRESS

/* Re-definition of CONSTANT_ADDRESS_P, which is true only when there
   are no SYMBOL_REFs for external symbols present.  */

static int
indirectable_constant_address_p (rtx x)
{
  if (!CONSTANT_ADDRESS_P (x))
    return 0;
  if (GET_CODE (x) == CONST && GET_CODE (XEXP ((x), 0)) == PLUS)
    x = XEXP (XEXP (x, 0), 0);
  if (GET_CODE (x) == SYMBOL_REF && !SYMBOL_REF_LOCAL_P (x))
    return 0;

  return 1;
}

#else /* not NO_EXTERNAL_INDIRECT_ADDRESS */

static int
indirectable_constant_address_p (rtx x)
{
  return CONSTANT_ADDRESS_P (x);
}

#endif /* not NO_EXTERNAL_INDIRECT_ADDRESS */

/* Nonzero if X is an address which can be indirected.  External symbols
   could be in a sharable image library, so we disallow those.  */

static int
indirectable_address_p(rtx x, int strict)
{
  if (indirectable_constant_address_p (x))
    return 1;
  if (BASE_REGISTER_P (x, strict))
    return 1;
  if (GET_CODE (x) == PLUS
      && BASE_REGISTER_P (XEXP (x, 0), strict)
      && indirectable_constant_address_p (XEXP (x, 1)))
    return 1;
  return 0;
}

/* Return 1 if x is a valid address not using indexing.
   (This much is the easy part.)  */
static int
nonindexed_address_p (rtx x, int strict)
{
  rtx xfoo0;
  if (GET_CODE (x) == REG)
    {
      extern rtx *reg_equiv_mem;
      if (! reload_in_progress
	  || reg_equiv_mem[REGNO (x)] == 0
	  || indirectable_address_p (reg_equiv_mem[REGNO (x)], strict))
	return 1;
    }
  if (indirectable_constant_address_p (x))
    return 1;
  if (indirectable_address_p (x, strict))
    return 1;
  xfoo0 = XEXP (x, 0);
  if (GET_CODE (x) == MEM && indirectable_address_p (xfoo0, strict))
    return 1;
  if ((GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC)
      && BASE_REGISTER_P (xfoo0, strict))
    return 1;
  return 0;
}

/* 1 if PROD is either a reg times size of mode MODE and MODE is less
   than or equal 8 bytes, or just a reg if MODE is one byte.  */

static int
index_term_p (rtx prod, enum machine_mode mode, int strict)
{
  rtx xfoo0, xfoo1;

  if (GET_MODE_SIZE (mode) == 1)
    return BASE_REGISTER_P (prod, strict);

  if (GET_CODE (prod) != MULT || GET_MODE_SIZE (mode) > 8)
    return 0;

  xfoo0 = XEXP (prod, 0);
  xfoo1 = XEXP (prod, 1);

  if (GET_CODE (xfoo0) == CONST_INT
      && INTVAL (xfoo0) == (int)GET_MODE_SIZE (mode)
      && INDEX_REGISTER_P (xfoo1, strict))
    return 1;

  if (GET_CODE (xfoo1) == CONST_INT
      && INTVAL (xfoo1) == (int)GET_MODE_SIZE (mode)
      && INDEX_REGISTER_P (xfoo0, strict))
    return 1;

  return 0;
}

/* Return 1 if X is the sum of a register
   and a valid index term for mode MODE.  */
static int
reg_plus_index_p (rtx x, enum machine_mode mode, int strict)
{
  rtx xfoo0, xfoo1;

  if (GET_CODE (x) != PLUS)
    return 0;

  xfoo0 = XEXP (x, 0);
  xfoo1 = XEXP (x, 1);

  if (BASE_REGISTER_P (xfoo0, strict) && index_term_p (xfoo1, mode, strict))
    return 1;

  if (BASE_REGISTER_P (xfoo1, strict) && index_term_p (xfoo0, mode, strict))
    return 1;

  return 0;
}

/* legitimate_address_p returns 1 if it recognizes an RTL expression "x"
   that is a valid memory address for an instruction.
   The MODE argument is the machine mode for the MEM expression
   that wants to use this address.  */
int
legitimate_address_p (enum machine_mode mode, rtx x, int strict)
{
  rtx xfoo0, xfoo1;

  if (nonindexed_address_p (x, strict))
    return 1;

  if (GET_CODE (x) != PLUS)
    return 0;

  /* Handle <address>[index] represented with index-sum outermost */

  xfoo0 = XEXP (x, 0);
  xfoo1 = XEXP (x, 1);

  if (index_term_p (xfoo0, mode, strict)
      && nonindexed_address_p (xfoo1, strict))
    return 1;

  if (index_term_p (xfoo1, mode, strict)
      && nonindexed_address_p (xfoo0, strict))
    return 1;

  /* Handle offset(reg)[index] with offset added outermost */

  if (indirectable_constant_address_p (xfoo0)
      && (BASE_REGISTER_P (xfoo1, strict)
          || reg_plus_index_p (xfoo1, mode, strict)))
    return 1;

  if (indirectable_constant_address_p (xfoo1)
      && (BASE_REGISTER_P (xfoo0, strict)
          || reg_plus_index_p (xfoo0, mode, strict)))
    return 1;

  return 0;
}

/* Return 1 if x (a legitimate address expression) has an effect that
   depends on the machine mode it is used for.  On the VAX, the predecrement
   and postincrement address depend thus (the amount of decrement or
   increment being the length of the operand) and all indexed address depend
   thus (because the index scale factor is the length of the operand).  */

int
vax_mode_dependent_address_p (rtx x)
{
  rtx xfoo0, xfoo1;

  if (GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
    return 1;
  if (GET_CODE (x) != PLUS)
    return 0;

  xfoo0 = XEXP (x, 0);
  xfoo1 = XEXP (x, 1);

  if (CONSTANT_ADDRESS_P (xfoo0) && GET_CODE (xfoo1) == REG)
    return 0;
  if (CONSTANT_ADDRESS_P (xfoo1) && GET_CODE (xfoo0) == REG)
    return 0;

  return 1;
}