ia64.md

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  [(set (match_operand:DI 0 "register_operand" "=r")
	(plus:DI (reg:DI 1) (match_operand 1 "sdata_symbolic_operand" "s")))]
  "reload_completed"
  "addl %0 = @gprel(%1), gp"
  [(set_attr "itanium_class" "ialu")])

(define_insn "*gprel64_offset"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))]
  "reload_completed"
  "movl %0 = @gprel(%1)"
  [(set_attr "itanium_class" "long_i")])

(define_expand "load_gprel64"
  [(set (match_operand:DI 0 "register_operand" "")
	(minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 2)))
   (set (match_dup 0)
	(plus:DI (match_dup 2) (match_dup 0)))]
  "reload_completed"
{
  operands[2] = pic_offset_table_rtx;
})

;; This is used as a placeholder for the return address during early
;; compilation.  We won't know where we've placed this until during
;; reload, at which point it can wind up in b0, a general register,
;; or memory.  The only safe destination under these conditions is a
;; general register.

(define_insn_and_split "*movdi_ret_addr"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(unspec:DI [(const_int 0)] UNSPEC_RET_ADDR))]
  ""
  "#"
  "reload_completed"
  [(const_int 0)]
{
  ia64_split_return_addr_rtx (operands[0]);
  DONE;
}
  [(set_attr "itanium_class" "ialu")])

(define_insn "*load_symptr_high"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(plus:DI (high:DI (match_operand 1 "got_symbolic_operand" "s"))
		 (match_operand:DI 2 "register_operand" "a")))]
  "reload_completed"
{
  if (HAVE_AS_LTOFFX_LDXMOV_RELOCS)
    return "%,addl %0 = @ltoffx(%1), %2";
  else
    return "%,addl %0 = @ltoff(%1), %2";
}
  [(set_attr "itanium_class" "ialu")])

(define_insn "*load_symptr_low"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
		   (match_operand 2 "got_symbolic_operand" "s")))]
  "reload_completed"
{
  if (HAVE_AS_LTOFFX_LDXMOV_RELOCS)
    return "%,ld8.mov %0 = [%1], %2";
  else
    return "%,ld8 %0 = [%1]";
}
  [(set_attr "itanium_class" "ld")])

(define_insn_and_split "load_dtpmod"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
		   UNSPEC_DTPMOD))]
  ""
  "#"
  "reload_completed"
  [(set (match_dup 0)
	(plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPMOD)
		 (match_dup 2)))
   (set (match_dup 0) (match_dup 3))]
{
  operands[2] = pic_offset_table_rtx;
  operands[3] = gen_const_mem (DImode, operands[0]);
})

(define_insn "*load_ltoff_dtpmod"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
			    UNSPEC_LTOFF_DTPMOD)
		 (match_operand:DI 2 "register_operand" "a")))]
  "reload_completed"
  "addl %0 = @ltoff(@dtpmod(%1)), %2"
  [(set_attr "itanium_class" "ialu")])

(define_expand "load_dtprel"
  [(set (match_operand:DI 0 "register_operand" "")
	(unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
		   UNSPEC_DTPREL))]
  ""
  "")

(define_insn "*load_dtprel64"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
		   UNSPEC_DTPREL))]
  "TARGET_TLS64"
  "movl %0 = @dtprel(%1)"
  [(set_attr "itanium_class" "long_i")])

(define_insn "*load_dtprel22"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
		   UNSPEC_DTPREL))]
  ""
  "addl %0 = @dtprel(%1), r0"
  [(set_attr "itanium_class" "ialu")])

(define_insn_and_split "*load_dtprel_gd"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
		   UNSPEC_DTPREL))]
  ""
  "#"
  "reload_completed"
  [(set (match_dup 0)
	(plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPREL)
		 (match_dup 2)))
   (set (match_dup 0) (match_dup 3))]
{
  operands[2] = pic_offset_table_rtx;
  operands[3] = gen_const_mem (DImode, operands[0]);
})

(define_insn "*load_ltoff_dtprel"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
			    UNSPEC_LTOFF_DTPREL)
		 (match_operand:DI 2 "register_operand" "a")))]
  ""
  "addl %0 = @ltoff(@dtprel(%1)), %2"
  [(set_attr "itanium_class" "ialu")])

(define_expand "add_dtprel"
  [(set (match_operand:DI 0 "register_operand" "")
	(plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
			    UNSPEC_DTPREL)
		 (match_operand:DI 2 "register_operand" "")))]
  "!TARGET_TLS64"
  "")

(define_insn "*add_dtprel14"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
			    UNSPEC_DTPREL)
		 (match_operand:DI 2 "register_operand" "r")))]
  "TARGET_TLS14"
  "adds %0 = @dtprel(%1), %2"
  [(set_attr "itanium_class" "ialu")])

(define_insn "*add_dtprel22"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
			    UNSPEC_DTPREL)
		 (match_operand:DI 2 "register_operand" "a")))]
  "TARGET_TLS22"
  "addl %0 = @dtprel(%1), %2"
  [(set_attr "itanium_class" "ialu")])

(define_expand "load_tprel"
  [(set (match_operand:DI 0 "register_operand" "")
	(unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
		   UNSPEC_TPREL))]
  ""
  "")

(define_insn "*load_tprel64"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
		   UNSPEC_TPREL))]
  "TARGET_TLS64"
  "movl %0 = @tprel(%1)"
  [(set_attr "itanium_class" "long_i")])

(define_insn "*load_tprel22"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
		   UNSPEC_TPREL))]
  ""
  "addl %0 = @tprel(%1), r0"
  [(set_attr "itanium_class" "ialu")])

(define_insn_and_split "*load_tprel_ie"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")]
		   UNSPEC_TPREL))]
  ""
  "#"
  "reload_completed"
  [(set (match_dup 0)
	(plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_TPREL)
		 (match_dup 2)))
   (set (match_dup 0) (match_dup 3))]
{
  operands[2] = pic_offset_table_rtx;
  operands[3] = gen_const_mem (DImode, operands[0]);
})

(define_insn "*load_ltoff_tprel"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(plus:DI (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")]
			    UNSPEC_LTOFF_TPREL)
		 (match_operand:DI 2 "register_operand" "a")))]
  ""
  "addl %0 = @ltoff(@tprel(%1)), %2"
  [(set_attr "itanium_class" "ialu")])

(define_expand "add_tprel"
  [(set (match_operand:DI 0 "register_operand" "")
	(plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
			    UNSPEC_TPREL)
		 (match_operand:DI 2 "register_operand" "")))]
  "!TARGET_TLS64"
  "")

(define_insn "*add_tprel14"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
			    UNSPEC_TPREL)
		 (match_operand:DI 2 "register_operand" "r")))]
  "TARGET_TLS14"
  "adds %0 = @tprel(%1), %2"
  [(set_attr "itanium_class" "ialu")])

(define_insn "*add_tprel22"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
			    UNSPEC_TPREL)
		 (match_operand:DI 2 "register_operand" "a")))]
  "TARGET_TLS22"
  "addl %0 = @tprel(%1), %2"
  [(set_attr "itanium_class" "ialu")])

;; With no offsettable memory references, we've got to have a scratch
;; around to play with the second word.  However, in order to avoid a
;; reload nightmare we lie, claim we don't need one, and fix it up
;; in ia64_split_tmode_move.
(define_expand "movti"
  [(set (match_operand:TI 0 "general_operand" "")
	(match_operand:TI 1 "general_operand" ""))]
  ""
{
  rtx op1 = ia64_expand_move (operands[0], operands[1]);
  if (!op1)
    DONE;
  operands[1] = op1;
})

(define_insn_and_split "*movti_internal"
  [(set (match_operand:TI 0 "destination_operand" "=r,   *fm,*x,*f,  Q")
	(match_operand:TI 1 "general_operand"     "r*fim,r,  Q, *fOQ,*f"))]
  "ia64_move_ok (operands[0], operands[1])"
  "@
   #
   #
   ldfp8 %X0 = %1%P1
   #
   #"
  "reload_completed && !ia64_load_pair_ok(operands[0], operands[1])"
  [(const_int 0)]
{
  ia64_split_tmode_move (operands);
  DONE;
}
  [(set_attr "itanium_class" "unknown,unknown,fldp,unknown,unknown")])

;; Floating Point Moves
;;
;; Note - Patterns for SF mode moves are compulsory, but
;; patterns for DF are optional, as GCC can synthesize them.

(define_expand "movsf"
  [(set (match_operand:SF 0 "general_operand" "")
	(match_operand:SF 1 "general_operand" ""))]
  ""
{
  rtx op1 = ia64_expand_move (operands[0], operands[1]);
  if (!op1)
    DONE;
  operands[1] = op1;
})

(define_insn "*movsf_internal"
  [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
	(match_operand:SF 1 "general_operand"     "fG,Q,fG,fG,*r,*r, m,*r"))]
  "ia64_move_ok (operands[0], operands[1])"
  "@
   mov %0 = %F1
   ldfs %0 = %1%P1
   stfs %0 = %F1%P0
   getf.s %0 = %F1
   setf.s %0 = %1
   mov %0 = %1
   ld4%O1 %0 = %1%P1
   st4%Q0 %0 = %1%P0"
  [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])

(define_expand "movdf"
  [(set (match_operand:DF 0 "general_operand" "")
	(match_operand:DF 1 "general_operand" ""))]
  ""
{
  rtx op1 = ia64_expand_move (operands[0], operands[1]);
  if (!op1)
    DONE;
  operands[1] = op1;
})

(define_insn "*movdf_internal"
  [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
	(match_operand:DF 1 "general_operand"     "fG,Q,fG,fG,*r,*r, m,*r"))]
  "ia64_move_ok (operands[0], operands[1])"
  "@
   mov %0 = %F1
   ldfd %0 = %1%P1
   stfd %0 = %F1%P0
   getf.d %0 = %F1
   setf.d %0 = %1
   mov %0 = %1
   ld8%O1 %0 = %1%P1
   st8%Q0 %0 = %1%P0"
  [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])

;; With no offsettable memory references, we've got to have a scratch
;; around to play with the second word if the variable winds up in GRs.
(define_expand "movxf"
  [(set (match_operand:XF 0 "general_operand" "")
	(match_operand:XF 1 "general_operand" ""))]
  ""
{
  if (ia64_expand_movxf_movrf (XFmode, operands))
    DONE;
})

;; ??? There's no easy way to mind volatile acquire/release semantics.

(define_insn "*movxf_internal"
  [(set (match_operand:XF 0 "destination_operand" "=f,f, m")
	(match_operand:XF 1 "general_operand"     "fG,m,fG"))]
  "ia64_move_ok (operands[0], operands[1])"
  "@
   mov %0 = %F1
   ldfe %0 = %1%P1
   stfe %0 = %F1%P0"
  [(set_attr "itanium_class" "fmisc,fld,stf")])

;; Same as for movxf, but for RFmode.
(define_expand "movrf"
  [(set (match_operand:RF 0 "general_operand" "")
	(match_operand:RF 1 "general_operand" ""))]
  ""
{
  if (ia64_expand_movxf_movrf (RFmode, operands))
    DONE;
})

(define_insn "*movrf_internal"
  [(set (match_operand:RF 0 "destination_operand" "=f,f, m")
	(match_operand:RF 1 "general_operand"     "fG,m,fG"))]
  "ia64_move_ok (operands[0], operands[1])"
  "@
   mov %0 = %F1
   ldf.fill %0 = %1%P1
   stf.spill %0 = %F1%P0"
  [(set_attr "itanium_class" "fmisc,fld,stf")])

;; Better code generation via insns that deal with TFmode register pairs
;; directly.  Same concerns apply as for TImode.
(define_expand "movtf"
  [(set (match_operand:TF 0 "general_operand" "")
	(match_operand:TF 1 "general_operand" ""))]
  ""
{
  rtx op1 = ia64_expand_move (operands[0], operands[1]);
  if (!op1)
    DONE;
  operands[1] = op1;
})

(define_insn_and_split "*movtf_internal"
  [(set (match_operand:TF 0 "destination_operand"  "=r,r,m")
	(match_operand:TF 1 "general_operand"      "ri,m,r"))]
  "ia64_move_ok (operands[0], operands[1])"
  "#"
  "reload_completed"
  [(const_int 0)]
{
  ia64_split_tmode_move (operands);
  DONE;
}
  [(set_attr "itanium_class" "unknown")
   (set_attr "predicable" "no")])


;; ::::::::::::::::::::
;; ::