ia64.h

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     (MODE) != BImode &&					\
     (MODE) != TFmode 						\
   : PR_REGNO_P (REGNO) ?					\
     (MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC	\
   : GR_REGNO_P (REGNO) ?					\
     (MODE) != CCImode && (MODE) != XFmode && (MODE) != XCmode	\
   : AR_REGNO_P (REGNO) ? (MODE) == DImode			\
   : BR_REGNO_P (REGNO) ? (MODE) == DImode			\
   : 0)

/* A C expression that is nonzero if it is desirable to choose register
   allocation so as to avoid move instructions between a value of mode MODE1
   and a value of mode MODE2.

   If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
   ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
   zero.  */
/* Don't tie integer and FP modes, as that causes us to get integer registers
   allocated for FP instructions.  XFmode only supported in FP registers so
   we can't tie it with any other modes.  */
#define MODES_TIEABLE_P(MODE1, MODE2)			\
  (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)	\
   && ((((MODE1) == XFmode) || ((MODE1) == XCmode))	\
       == (((MODE2) == XFmode) || ((MODE2) == XCmode)))	\
   && (((MODE1) == BImode) == ((MODE2) == BImode)))

/* Specify the modes required to caller save a given hard regno.
   We need to ensure floating pt regs are not saved as DImode.  */

#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
  ((FR_REGNO_P (REGNO) && (NREGS) == 1) ? XFmode        \
   : choose_hard_reg_mode ((REGNO), (NREGS), false))

/* Handling Leaf Functions */

/* A C initializer for a vector, indexed by hard register number, which
   contains 1 for a register that is allowable in a candidate for leaf function
   treatment.  */
/* ??? This might be useful.  */
/* #define LEAF_REGISTERS */

/* A C expression whose value is the register number to which REGNO should be
   renumbered, when a function is treated as a leaf function.  */
/* ??? This might be useful.  */
/* #define LEAF_REG_REMAP(REGNO) */


/* Register Classes */

/* An enumeral type that must be defined with all the register class names as
   enumeral values.  `NO_REGS' must be first.  `ALL_REGS' must be the last
   register class, followed by one more enumeral value, `LIM_REG_CLASSES',
   which is not a register class but rather tells how many classes there
   are.  */
/* ??? When compiling without optimization, it is possible for the only use of
   a pseudo to be a parameter load from the stack with a REG_EQUIV note.
   Regclass handles this case specially and does not assign any costs to the
   pseudo.  The pseudo then ends up using the last class before ALL_REGS.
   Thus we must not let either PR_REGS or BR_REGS be the last class.  The
   testcase for this is gcc.c-torture/execute/va-arg-7.c.  */
enum reg_class
{
  NO_REGS,
  PR_REGS,
  BR_REGS,
  AR_M_REGS,
  AR_I_REGS,
  ADDL_REGS,
  GR_REGS,
  FP_REGS,
  FR_REGS,
  GR_AND_BR_REGS,
  GR_AND_FR_REGS,
  ALL_REGS,
  LIM_REG_CLASSES
};

#define GENERAL_REGS GR_REGS

/* The number of distinct register classes.  */
#define N_REG_CLASSES ((int) LIM_REG_CLASSES)

/* An initializer containing the names of the register classes as C string
   constants.  These names are used in writing some of the debugging dumps.  */
#define REG_CLASS_NAMES \
{ "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \
  "ADDL_REGS", "GR_REGS", "FP_REGS", "FR_REGS", \
  "GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" }

/* An initializer containing the contents of the register classes, as integers
   which are bit masks.  The Nth integer specifies the contents of class N.
   The way the integer MASK is interpreted is that register R is in the class
   if `MASK & (1 << R)' is 1.  */
#define REG_CLASS_CONTENTS \
{ 							\
  /* NO_REGS.  */					\
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000,	\
    0x00000000, 0x00000000, 0x00000000, 0x00000000,	\
    0x00000000, 0x00000000, 0x0000 },			\
  /* PR_REGS.  */					\
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000,	\
    0x00000000, 0x00000000, 0x00000000, 0x00000000,	\
    0xFFFFFFFF, 0xFFFFFFFF, 0x0000 },			\
  /* BR_REGS.  */					\
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000,	\
    0x00000000, 0x00000000, 0x00000000, 0x00000000,	\
    0x00000000, 0x00000000, 0x00FF },			\
  /* AR_M_REGS.  */					\
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000,	\
    0x00000000, 0x00000000, 0x00000000, 0x00000000,	\
    0x00000000, 0x00000000, 0x0600 },			\
  /* AR_I_REGS.  */					\
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000,	\
    0x00000000, 0x00000000, 0x00000000, 0x00000000,	\
    0x00000000, 0x00000000, 0x3800 },			\
  /* ADDL_REGS.  */					\
  { 0x0000000F, 0x00000000, 0x00000000, 0x00000000,	\
    0x00000000, 0x00000000, 0x00000000, 0x00000000,	\
    0x00000000, 0x00000000, 0x0000 },			\
  /* GR_REGS.  */					\
  { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,	\
    0x00000000, 0x00000000, 0x00000000, 0x00000000,	\
    0x00000000, 0x00000000, 0x0100 },			\
  /* FP_REGS.  */					\
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000,	\
    0x7FFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF,	\
    0x00000000, 0x00000000, 0x0000 },			\
  /* FR_REGS.  */					\
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000,	\
    0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,	\
    0x00000000, 0x00000000, 0x0000 },			\
  /* GR_AND_BR_REGS.  */				\
  { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,	\
    0x00000000, 0x00000000, 0x00000000, 0x00000000,	\
    0x00000000, 0x00000000, 0x01FF },			\
  /* GR_AND_FR_REGS.  */				\
  { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,	\
    0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,	\
    0x00000000, 0x00000000, 0x0100 },			\
  /* ALL_REGS.  */					\
  { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,	\
    0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,	\
    0xFFFFFFFF, 0xFFFFFFFF, 0x3FFF },			\
}

/* A C expression whose value is a register class containing hard register
   REGNO.  In general there is more than one such class; choose a class which
   is "minimal", meaning that no smaller class also contains the register.  */
/* The NO_REGS case is primarily for the benefit of rws_access_reg, which
   may call here with private (invalid) register numbers, such as
   REG_VOLATILE.  */
#define REGNO_REG_CLASS(REGNO) \
(ADDL_REGNO_P (REGNO) ? ADDL_REGS	\
 : GENERAL_REGNO_P (REGNO) ? GR_REGS	\
 : FR_REGNO_P (REGNO) ? (REGNO) != R_FR (31) \
			&& (REGNO) != R_FR(127) ? FP_REGS : FR_REGS \
 : PR_REGNO_P (REGNO) ? PR_REGS		\
 : BR_REGNO_P (REGNO) ? BR_REGS		\
 : AR_M_REGNO_P (REGNO) ? AR_M_REGS	\
 : AR_I_REGNO_P (REGNO) ? AR_I_REGS	\
 : NO_REGS)

/* A macro whose definition is the name of the class to which a valid base
   register must belong.  A base register is one used in an address which is
   the register value plus a displacement.  */
#define BASE_REG_CLASS GENERAL_REGS

/* A macro whose definition is the name of the class to which a valid index
   register must belong.  An index register is one used in an address where its
   value is either multiplied by a scale factor or added to another register
   (as well as added to a displacement).  This is needed for POST_MODIFY.  */
#define INDEX_REG_CLASS GENERAL_REGS

/* A C expression which defines the machine-dependent operand constraint
   letters for register classes.  If CHAR is such a letter, the value should be
   the register class corresponding to it.  Otherwise, the value should be
   `NO_REGS'.  The register letter `r', corresponding to class `GENERAL_REGS',
   will not be passed to this macro; you do not need to handle it.  */

#define REG_CLASS_FROM_LETTER(CHAR) \
((CHAR) == 'f' ? FR_REGS		\
 : (CHAR) == 'a' ? ADDL_REGS		\
 : (CHAR) == 'b' ? BR_REGS		\
 : (CHAR) == 'c' ? PR_REGS		\
 : (CHAR) == 'd' ? AR_M_REGS		\
 : (CHAR) == 'e' ? AR_I_REGS		\
 : (CHAR) == 'x' ? FP_REGS		\
 : NO_REGS)

/* A C expression which is nonzero if register number NUM is suitable for use
   as a base register in operand addresses.  It may be either a suitable hard
   register or a pseudo register that has been allocated such a hard reg.  */
#define REGNO_OK_FOR_BASE_P(REGNO) \
  (GENERAL_REGNO_P (REGNO) || GENERAL_REGNO_P (reg_renumber[REGNO]))

/* A C expression which is nonzero if register number NUM is suitable for use
   as an index register in operand addresses.  It may be either a suitable hard
   register or a pseudo register that has been allocated such a hard reg.
   This is needed for POST_MODIFY.  */
#define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)

/* A C expression that places additional restrictions on the register class to
   use when it is necessary to copy value X into a register in class CLASS.
   The value is a register class; perhaps CLASS, or perhaps another, smaller
   class.  */

#define PREFERRED_RELOAD_CLASS(X, CLASS) \
  ia64_preferred_reload_class (X, CLASS)

/* You should define this macro to indicate to the reload phase that it may
   need to allocate at least one register for a reload in addition to the
   register to contain the data.  Specifically, if copying X to a register
   CLASS in MODE requires an intermediate register, you should define this
   to return the largest register class all of whose registers can be used
   as intermediate registers or scratch registers.  */

#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
 ia64_secondary_reload_class (CLASS, MODE, X)

/* Certain machines have the property that some registers cannot be copied to
   some other registers without using memory.  Define this macro on those
   machines to be a C expression that is nonzero if objects of mode M in
   registers of CLASS1 can only be copied to registers of class CLASS2 by
   storing a register of CLASS1 into memory and loading that memory location
   into a register of CLASS2.  */

#if 0
/* ??? May need this, but since we've disallowed XFmode in GR_REGS,
   I'm not quite sure how it could be invoked.  The normal problems
   with unions should be solved with the addressof fiddling done by
   movxf and friends.  */
#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE)			\
  (((MODE) == XFmode || (MODE) == XCmode)				\
   && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS)			\
       || ((CLASS1) == FR_REGS && (CLASS2) == GR_REGS)))
#endif

/* A C expression for the maximum number of consecutive registers of
   class CLASS needed to hold a value of mode MODE.
   This is closely related to the macro `HARD_REGNO_NREGS'.  */

#define CLASS_MAX_NREGS(CLASS, MODE) \
  ((MODE) == BImode && (CLASS) == PR_REGS ? 2			\
   : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XFmode) ? 1 \
   : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XCmode) ? 2 \
   : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)

/* In FP regs, we can't change FP values to integer values and vice versa,
   but we can change e.g. DImode to SImode, and V2SFmode into DImode.  */

#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) 		\
  (SCALAR_FLOAT_MODE_P (FROM) != SCALAR_FLOAT_MODE_P (TO)	\
   ? reg_classes_intersect_p (CLASS, FR_REGS) : 0)

/* A C expression that defines the machine-dependent operand constraint
   letters (`I', `J', `K', .. 'P') that specify particular ranges of
   integer values.  */

/* 14 bit signed immediate for arithmetic instructions.  */
#define CONST_OK_FOR_I(VALUE) \
  ((unsigned HOST_WIDE_INT)(VALUE) + 0x2000 < 0x4000)
/* 22 bit signed immediate for arith instructions with r0/r1/r2/r3 source.  */
#define CONST_OK_FOR_J(VALUE) \
  ((unsigned HOST_WIDE_INT)(VALUE) + 0x200000 < 0x400000)
/* 8 bit signed immediate for logical instructions.  */
#define CONST_OK_FOR_K(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x80 < 0x100)
/* 8 bit adjusted signed immediate for compare pseudo-ops.  */
#define CONST_OK_FOR_L(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x7F < 0x100)
/* 6 bit unsigned immediate for shift counts.  */
#define CONST_OK_FOR_M(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) < 0x40)
/* 9 bit signed immediate for load/store post-increments.  */
#define CONST_OK_FOR_N(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x100 < 0x200)
/* 0 for r0.  Used by Linux kernel, do not change.  */
#define CONST_OK_FOR_O(VALUE) ((VALUE) == 0)
/* 0 or -1 for dep instruction.  */
#define CONST_OK_FOR_P(VALUE) ((VALUE) == 0 || (VALUE) == -1)

#define CONST_OK_FOR_LETTER_P(VALUE, C) \
  ia64_const_ok_for_letter_p (VALUE, C)

/* A C expression that defines the machine-dependent operand constraint letters
   (`G', `H') that specify particular ranges of `const_double' values.  */

/* 0.0 and 1.0 for fr0 and fr1.  */
#define CONST_DOUBLE_OK_FOR_G(VALUE) \
  ((VALUE) == CONST0_RTX (GET_MODE (VALUE))	\
   || (VALUE) == CONST1_RTX (GET_MODE (VALUE)))

#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
  ia64_const_double_ok_for_letter_p (VALUE, C)

/* A C expression that defines the optional machine-dependent constraint
   letters (`Q', `R', `S', `T', `U') that can be used to segregate specific
   types of operands, usually memory references, for the target machine.  */

#define EXTRA_CONSTRAINT(VALUE, C) \
  ia64_extra_constraint (VALUE, C)

/* Document the constraints that can accept reloaded memory operands.  This is
   needed by the extended asm support, and by reload.  'Q' accepts mem, but
   only non-volatile mem.  Since we can't reload a volatile mem into a
   non-volatile mem, it can not be listed here.  */

#define EXTRA_MEMORY_CONSTRAINT(C, STR)  ((C) == 'S')

/* Basic Stack Layout */

/* Define this macro if pushing a word onto the stack moves the stack pointer
   to a smaller address.  */
#define STACK_GROWS_DOWNWARD 1

/* Define this macro to nonzero if the addresses of local variable slots
   are at negative offsets from the frame pointer.  */
#define FRAME_GROWS_DOWNWARD 0

/* Offset from the frame pointer to the first local variable slot to
   be allocated.  */
#define STARTING_FRAME_OFFSET 0

/* Offset from the stack pointer register to the first location at which
   outgoing arguments are placed.  If not specified, the default value of zero
   is used.  This is the proper value for most machines.  */
/* IA64 has a 16 byte scratch area that is at the bottom of the stack.  */
#define STACK_POINTER_OFFSET 16

/* Offset from the argument pointer register to the first argument's address.
   On some machines it may depend on the data type of the function.  */