itanium2.md

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;; They are consequences of Itanium2 microarchitecture.  They also
;; describe the following rules mentioned in Itanium2
;; microarchitecture: rules mentioned in Itanium2 microarchitecture:
;; o "BBB/MBB: Always splits issue after either of these bundles".
;; o "MIB BBB: Split issue after the first bundle in this pair".
(exclusion_set
   "2b_0b.bb,2b_0bb.b,2b_0bbb.,2b_0m.bb,2b_0mb.b,2b_0mbb."
   "2b_1m.ii,2b_1m.mi,2b_1m.fi,2b_1m.mf,2b_1b.bb,2b_1m.bb,\
    2b_1m.ib,2b_1m.mb,2b_1m.fb,2b_1m.lx")
(exclusion_set "2b_0m.ib,2b_0mi.b,2b_0mib." "2b_1b.bb")

;;; "MIB/MFB/MMB: Splits issue after any of these bundles unless the
;;; B-slot contains a nop.b or a brp instruction".
;;;   "The B in an MIB/MFB/MMB bundle disperses to B0 if it is a brp or
;;; nop.b, otherwise it disperses to B2".
(final_absence_set
   "2b_1m.ii, 2b_1m.mi, 2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb,\
    2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx"
   "2b_0mib. 2b_ub2, 2b_0mfb. 2b_ub2, 2b_0mmb. 2b_ub2")

;; This is necessary to start new processor cycle when we meet stop bit.
(define_cpu_unit "2b_stop" "twob")
(final_absence_set
   "2b_0m.ii,2b_0mi.i,2b_0mii.,2b_0m.mi,2b_0mm.i,2b_0mmi.,\
    2b_0m.fi,2b_0mf.i,2b_0mfi.,\
    2b_0m.mf,2b_0mm.f,2b_0mmf.,2b_0b.bb,2b_0bb.b,2b_0bbb.,\
    2b_0m.bb,2b_0mb.b,2b_0mbb.,\
    2b_0m.ib,2b_0mi.b,2b_0mib.,2b_0m.mb,2b_0mm.b,2b_0mmb.,\
    2b_0m.fb,2b_0mf.b,2b_0mfb.,2b_0m.lx,2b_0mlx., \
    2b_1m.ii,2b_1mi.i,2b_1mii.,2b_1m.mi,2b_1mm.i,2b_1mmi.,\
    2b_1m.fi,2b_1mf.i,2b_1mfi.,\
    2b_1m.mf,2b_1mm.f,2b_1mmf.,2b_1b.bb,2b_1bb.b,2b_1bbb.,\
    2b_1m.bb,2b_1mb.b,2b_1mbb.,\
    2b_1m.ib,2b_1mi.b,2b_1mib.,2b_1m.mb,2b_1mm.b,2b_1mmb.,\
    2b_1m.fb,2b_1mf.b,2b_1mfb.,2b_1m.lx,2b_1mlx."
   "2b_stop")

;;   The issue logic can reorder M slot insns between different subtypes
;; but cannot reorder insn within the same subtypes.  The following
;; constraint is enough to describe this.
(final_presence_set "2b_um1" "2b_um0")
(final_presence_set "2b_um3" "2b_um2")

;;   The insn in the 1st I slot of the two bundle issue group will issue
;; to I0.  The second I slot insn will issue to I1.
(final_presence_set "2b_ui1" "2b_ui0")

;;  For exceptions of I insns:
(define_cpu_unit "2b_only_ui0" "twob")
(final_absence_set "2b_only_ui0"  "2b_ui1")

;; Insns

(define_reservation "2b_M"
  "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\
     |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\
    |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\
      |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\
    |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\
    |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\
   +(2b_um0|2b_um1|2b_um2|2b_um3)")

(define_reservation "2b_M_only_um0"
  "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\
     |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\
    |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\
      |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\
    |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\
    |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\
   +2b_um0")

(define_reservation "2b_M_only_um2"
  "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\
     |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\
    |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\
      |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\
    |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\
    |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\
   +2b_um2")

(define_reservation "2b_M_only_um01"
  "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\
     |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\
    |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\
      |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\
    |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\
    |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\
   +(2b_um0|2b_um1)")

(define_reservation "2b_M_only_um23"
  "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\
     |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\
    |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\
      |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\
    |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\
    |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\
   +(2b_um2|2b_um3)")

;; I instruction is dispersed to the lowest numbered I unit
;; not already in use.  Remember about possible splitting.
(define_reservation "2b_I"
  "2b_0mi.i+2_2+2b_ui0|2b_0mii.+2_3+(2b_ui0|2b_ui1)|2b_0mmi.+2_3+2b_ui0\
   |2b_0mfi.+2_3+2b_ui0|2b_0mi.b+2_2+2b_ui0\
   |(2b_1mi.i+2_5|2b_1mi.b+2_5)+(2b_ui0|2b_ui1)\
   |(2b_1mii.|2b_1mmi.|2b_1mfi.)+2_6+(2b_ui0|2b_ui1)")

;; "An F slot in the 1st bundle disperses to F0".
;; "An F slot in the 2st bundle disperses to F1".
(define_reservation "2b_F"
   "2b_0mf.i+2_2+2b_uf0|2b_0mmf.+2_3+2b_uf0|2b_0mf.b+2_2+2b_uf0\
    |2b_1mf.i+2_5+2b_uf1|2b_1mmf.+2_6+2b_uf1|2b_1mf.b+2_5+2b_uf1")

;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B
;;; unit. That is, a B slot in 1st position is dispersed to B0.  In the
;;; 2nd position it is dispersed to B2".
(define_reservation "2b_NB"
    "2b_0b.bb+2_1+2b_unb0|2b_0bb.b+2_2+2b_unb1|2b_0bbb.+2_3+2b_unb2\
     |2b_0mb.b+2_2+2b_unb1|2b_0mbb.+2_3+2b_unb2\
     |2b_0mib.+2_3+2b_unb0|2b_0mmb.+2_3+2b_unb0|2b_0mfb.+2_3+2b_unb0\
     |2b_1b.bb+2_4+2b_unb0|2b_1bb.b+2_5+2b_unb1\
     |2b_1bbb.+2_6+2b_unb2|2b_1mb.b+2_5+2b_unb1|2b_1mbb.+2_6+2b_unb2\
     |2b_1mib.+2_6+2b_unb0|2b_1mmb.+2_6+2b_unb0|2b_1mfb.+2_6+2b_unb0")

(define_reservation "2b_B"
   "2b_0b.bb+2_1+2b_ub0|2b_0bb.b+2_2+2b_ub1|2b_0bbb.+2_3+2b_ub2\
    |2b_0mb.b+2_2+2b_ub1|2b_0mbb.+2_3+2b_ub2|2b_0mib.+2_3+2b_ub2\
    |2b_0mfb.+2_3+2b_ub2|2b_1b.bb+2_4+2b_ub0|2b_1bb.b+2_5+2b_ub1\
    |2b_1bbb.+2_6+2b_ub2|2b_1mb.b+2_5+2b_ub1\
    |2b_1mib.+2_6+2b_ub2|2b_1mmb.+2_6+2b_ub2|2b_1mfb.+2_6+2b_ub2")

;;   For the MLI template, the I slot insn is always assigned to port I0
;; if it is in the first bundle or it is assigned to port I1 if it is in
;; the second bundle.
(define_reservation "2b_L"
                    "2b_0mlx.+2_3+2b_ui0+2b_uf0|2b_1mlx.+2_6+2b_ui1+2b_uf1")

;;   Should we describe that A insn in I slot can be issued into M
;; ports?  I think it is not necessary because of multipass
;; scheduling.  For example, the multipass scheduling could use
;; MMI-MMI instead of MII-MII where the two last I slots contain A
;; insns (even if the case is complicated by use-def conflicts).
;;
;; In any case we could describe it as
;;    (define_cpu_unit "2b_ui1_0pres,2b_ui1_1pres,2b_ui1_2pres,2b_ui1_3pres"
;;                     "twob")
;;    (final_presence_set "2b_ui1_0pres,2b_ui1_1pres,2b_ui1_2pres,2b_ui1_3pres"
;;                        "2b_ui1")
;;    (define_reservation "b_A"
;;       "b_M|b_I\
;;        |(2b_1mi.i+2_5|2b_1mii.+2_6|2b_1mmi.+2_6|2b_1mfi.+2_6|2b_1mi.b+2_5)\
;;         +(2b_um0|2b_um1|2b_um2|2b_um3)\
;;         +(2b_ui1_0pres|2b_ui1_1pres|2b_ui1_2pres|2b_ui1_3pres)")

(define_reservation "2b_A" "2b_M|2b_I")

;; We assume that there is no insn issued on the same cycle as the
;; unknown insn.
(define_cpu_unit "2b_empty" "twob")
(exclusion_set "2b_empty"
    "2b_0m.ii,2b_0m.mi,2b_0m.fi,2b_0m.mf,2b_0b.bb,2b_0m.bb,\
     2b_0m.ib,2b_0m.mb,2b_0m.fb,2b_0m.lx,2b_0mm.i")

(define_cpu_unit
   "2b_0m_bs, 2b_0mi_bs, 2b_0mm_bs, 2b_0mf_bs, 2b_0b_bs, 2b_0bb_bs, 2b_0mb_bs"
   "twob")
(define_cpu_unit
   "2b_1m_bs, 2b_1mi_bs, 2b_1mm_bs, 2b_1mf_bs, 2b_1b_bs, 2b_1bb_bs, 2b_1mb_bs"
   "twob")

(define_cpu_unit "2b_m_cont, 2b_mi_cont, 2b_mm_cont, 2b_mf_cont, 2b_mb_cont,\
	          2b_b_cont, 2b_bb_cont" "twob")

;; For stop in the middle of the bundles.
(define_cpu_unit "2b_m_stop, 2b_m0_stop, 2b_m1_stop, 2b_0mmi_cont" "twob")
(define_cpu_unit "2b_mi_stop, 2b_mi0_stop, 2b_mi1_stop, 2b_0mii_cont" "twob")

(final_presence_set "2b_0m_bs"
   "2b_0m.ii, 2b_0m.mi, 2b_0m.mf, 2b_0m.fi, 2b_0m.bb,\
    2b_0m.ib, 2b_0m.fb, 2b_0m.mb, 2b_0m.lx")
(final_presence_set "2b_1m_bs"
   "2b_1m.ii, 2b_1m.mi, 2b_1m.mf, 2b_1m.fi, 2b_1m.bb,\
    2b_1m.ib, 2b_1m.fb, 2b_1m.mb, 2b_1m.lx")
(final_presence_set "2b_0mi_bs"  "2b_0mi.i, 2b_0mi.i")
(final_presence_set "2b_1mi_bs"  "2b_1mi.i, 2b_1mi.i")
(final_presence_set "2b_0mm_bs"  "2b_0mm.i, 2b_0mm.f, 2b_0mm.b")
(final_presence_set "2b_1mm_bs"  "2b_1mm.i, 2b_1mm.f, 2b_1mm.b")
(final_presence_set "2b_0mf_bs"  "2b_0mf.i, 2b_0mf.b")
(final_presence_set "2b_1mf_bs"  "2b_1mf.i, 2b_1mf.b")
(final_presence_set "2b_0b_bs"  "2b_0b.bb")
(final_presence_set "2b_1b_bs"  "2b_1b.bb")
(final_presence_set "2b_0bb_bs"  "2b_0bb.b")
(final_presence_set "2b_1bb_bs"  "2b_1bb.b")
(final_presence_set "2b_0mb_bs"  "2b_0mb.b")
(final_presence_set "2b_1mb_bs"  "2b_1mb.b")

(exclusion_set "2b_0m_bs"
   "2b_0mi.i, 2b_0mm.i, 2b_0mm.f, 2b_0mf.i, 2b_0mb.b,\
    2b_0mi.b, 2b_0mf.b, 2b_0mm.b, 2b_0mlx., 2b_m0_stop")
(exclusion_set "2b_1m_bs"
   "2b_1mi.i, 2b_1mm.i, 2b_1mm.f, 2b_1mf.i, 2b_1mb.b,\
    2b_1mi.b, 2b_1mf.b, 2b_1mm.b, 2b_1mlx., 2b_m1_stop")
(exclusion_set "2b_0mi_bs"  "2b_0mii., 2b_0mib., 2b_mi0_stop")
(exclusion_set "2b_1mi_bs"  "2b_1mii., 2b_1mib., 2b_mi1_stop")
(exclusion_set "2b_0mm_bs"  "2b_0mmi., 2b_0mmf., 2b_0mmb.")
(exclusion_set "2b_1mm_bs"  "2b_1mmi., 2b_1mmf., 2b_1mmb.")
(exclusion_set "2b_0mf_bs"  "2b_0mfi., 2b_0mfb.")
(exclusion_set "2b_1mf_bs"  "2b_1mfi., 2b_1mfb.")
(exclusion_set "2b_0b_bs"  "2b_0bb.b")
(exclusion_set "2b_1b_bs"  "2b_1bb.b")
(exclusion_set "2b_0bb_bs"  "2b_0bbb.")
(exclusion_set "2b_1bb_bs"  "2b_1bbb.")
(exclusion_set "2b_0mb_bs"  "2b_0mbb.")
(exclusion_set "2b_1mb_bs"  "2b_1mbb.")

(exclusion_set
   "2b_0m_bs, 2b_0mi_bs, 2b_0mm_bs, 2b_0mf_bs, 2b_0b_bs, 2b_0bb_bs, 2b_0mb_bs,
    2b_1m_bs, 2b_1mi_bs, 2b_1mm_bs, 2b_1mf_bs, 2b_1b_bs, 2b_1bb_bs, 2b_1mb_bs"
   "2b_stop")

(final_presence_set
   "2b_0mi.i, 2b_0mm.i, 2b_0mf.i, 2b_0mm.f, 2b_0mb.b,\
    2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx."
   "2b_m_cont")
(final_presence_set "2b_0mii., 2b_0mib." "2b_mi_cont")
(final_presence_set "2b_0mmi., 2b_0mmf., 2b_0mmb." "2b_mm_cont")
(final_presence_set "2b_0mfi., 2b_0mfb." "2b_mf_cont")
(final_presence_set "2b_0bb.b" "2b_b_cont")
(final_presence_set "2b_0bbb." "2b_bb_cont")
(final_presence_set "2b_0mbb." "2b_mb_cont")

(exclusion_set
   "2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\
    2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx"
   "2b_m_cont, 2b_mi_cont, 2b_mm_cont, 2b_mf_cont,\
    2b_mb_cont, 2b_b_cont, 2b_bb_cont")

(exclusion_set "2b_empty"
               "2b_m_cont,2b_mi_cont,2b_mm_cont,2b_mf_cont,\
                2b_mb_cont,2b_b_cont,2b_bb_cont")

;; For m;mi bundle
(final_presence_set "2b_m0_stop" "2b_0m.mi")
(final_presence_set "2b_0mm.i" "2b_0mmi_cont")
(exclusion_set "2b_0mmi_cont"
   "2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\
    2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx")
(exclusion_set "2b_m0_stop" "2b_0mm.i")
(final_presence_set "2b_m1_stop" "2b_1m.mi")
(exclusion_set "2b_m1_stop" "2b_1mm.i")
(final_presence_set "2b_m_stop" "2b_m0_stop, 2b_m1_stop")

;; For mi;i bundle
(final_presence_set "2b_mi0_stop" "2b_0mi.i")
(final_presence_set "2b_0mii." "2b_0mii_cont")
(exclusion_set "2b_0mii_cont"
   "2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\
    2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx")
(exclusion_set "2b_mi0_stop" "2b_0mii.")
(final_presence_set "2b_mi1_stop" "2b_1mi.i")
(exclusion_set "2b_mi1_stop" "2b_1mii.")
(final_presence_set "2b_mi_stop" "2b_mi0_stop, 2b_mi1_stop")

(final_absence_set
   "2b_0m.ii,2b_0mi.i,2b_0mii.,2b_0m.mi,2b_0mm.i,2b_0mmi.,\
    2b_0m.fi,2b_0mf.i,2b_0mfi.,2b_0m.mf,2b_0mm.f,2b_0mmf.,\
    2b_0b.bb,2b_0bb.b,2b_0bbb.,2b_0m.bb,2b_0mb.b,2b_0mbb.,\
    2b_0m.ib,2b_0mi.b,2b_0mib.,2b_0m.mb,2b_0mm.b,2b_0mmb.,\
    2b_0m.fb,2b_0mf.b,2b_0mfb.,2b_0m.lx,2b_0mlx., \
    2b_1m.ii,2b_1mi.i,2b_1mii.,2b_1m.mi,2b_1mm.i,2b_1mmi.,\
    2b_1m.fi,2b_1mf.i,2b_1mfi.,2b_1m.mf,2b_1mm.f,2b_1mmf.,\
    2b_1b.bb,2b_1bb.b,2b_1bbb.,2b_1m.bb,2b_1mb.b,2b_1mbb.,\
    2b_1m.ib,2b_1mi.b,2b_1mib.,2b_1m.mb,2b_1mm.b,2b_1mmb.,\
    2b_1m.fb,2b_1mf.b,2b_1mfb.,2b_1m.lx,2b_1mlx."
   "2b_m0_stop,2b_m1_stop,2b_mi0_stop,2b_mi1_stop")

(define_insn_reservation "2b_stop_bit" 0
  (and (and (eq_attr "cpu" "itanium2")
            (eq_attr "itanium_class" "stop_bit"))
       (ne (symbol_ref "bundling_p") (const_int 0)))
  "2b_stop|2b_m0_stop|2b_m1_stop|2b_mi0_stop|2b_mi1_stop")
(define_insn_reservation "2b_br"      0
  (and (and (eq_attr "cpu" "itanium2")
            (eq_attr "itanium_class" "br"))
       (ne (symbol_ref "bundling_p") (const_int 0))) "2b_B")
(define_insn_reservation "2b_scall"   0
  (and (and (eq_attr "cpu" "itanium2")
            (eq_attr "itanium_class" "scall"))
       (ne (symbol_ref "bundling_p") (const_int 0))) "2b_B")
(define_insn_reservation "2b_fcmp"    2
  (and (and (eq_attr "cpu" "itanium2")
            (eq_attr "itanium_class" "fcmp"))
       (ne (symbol_ref "bundling_p") (const_int 0))) "2b_F")
(define_insn_reservation "2b_fcvtfx"  4
  (and (and (eq_attr "cpu" "itanium2")
            (eq_attr "itanium_class" "fcvtfx"))
       (ne (symbol_ref "bundling_p") (const_int 0))) "2b_F")
(define_insn_reservation "2b_fld"     6
  (and (and (eq_attr "cpu" "itanium2")
            (eq_attr "itanium_class" "fld"))
       (ne (symbol_ref "bundling_p") (const_int 0))) "2b_M")
(define_insn_reservation "2b_fldp"    6
  (and (and (eq_attr "cpu" "itanium2")
            (eq_attr "itanium_class" "fldp"))
       (ne (symbol_ref "bundling_p") (const_int 0)))
  "2b_M_only_um01")
(define_insn_reservation "2b_fmac"    4
  (and (and (eq_attr "cpu" "itanium2")
            (eq_attr "itanium_class" "fmac"))
       (ne (symbol_ref "bundling_p") (const_int 0))) "2b_F")
(define_insn_reservation "2b_fmisc"   4
  (and (and (eq_at