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|1b_1bbb.+1_6+1b_ub2|1b_1mb.b+1_5+1b_ub1\ |1b_1mib.+1_6+1b_ub2|1b_1mmb.+1_6+1b_ub2|1b_1mfb.+1_6+1b_ub2")(define_reservation "1b_L" "1b_0mlx.+1_3+1b_ui0+1b_uf0\ |1b_1mlx.+1_6+(1b_ui0|1b_ui1)+1b_uf1");; We assume that there is no insn issued on the same cycle as unknown insn.(define_cpu_unit "1b_empty" "oneb")(exclusion_set "1b_empty" "1b_0m.ii,1b_0m.mi,1b_0m.fi,1b_0m.mf,1b_0b.bb,1b_0m.bb,\ 1b_0m.ib,1b_0m.mb,1b_0m.fb,1b_0m.lx")(define_cpu_unit "1b_0m_bs, 1b_0mi_bs, 1b_0mm_bs, 1b_0mf_bs, 1b_0b_bs, 1b_0bb_bs, 1b_0mb_bs" "oneb")(define_cpu_unit "1b_1m_bs, 1b_1mi_bs, 1b_1mm_bs, 1b_1mf_bs, 1b_1b_bs, 1b_1bb_bs, 1b_1mb_bs" "oneb")(define_cpu_unit "1b_m_cont, 1b_mi_cont, 1b_mm_cont, 1b_mf_cont, 1b_mb_cont,\ 1b_b_cont, 1b_bb_cont" "oneb");; For stop in the middle of the bundles.(define_cpu_unit "1b_m_stop, 1b_m0_stop, 1b_m1_stop, 1b_0mmi_cont" "oneb")(define_cpu_unit "1b_mi_stop, 1b_mi0_stop, 1b_mi1_stop, 1b_0mii_cont" "oneb")(final_presence_set "1b_0m_bs" "1b_0m.ii, 1b_0m.mi, 1b_0m.mf, 1b_0m.fi, 1b_0m.bb,\ 1b_0m.ib, 1b_0m.fb, 1b_0m.mb, 1b_0m.lx")(final_presence_set "1b_1m_bs" "1b_1m.ii, 1b_1m.mi, 1b_1m.fi, 1b_1m.bb, 1b_1m.ib, 1b_1m.fb, 1b_1m.mb,\ 1b_1m.lx")(final_presence_set "1b_0mi_bs" "1b_0mi.i, 1b_0mi.i")(final_presence_set "1b_1mi_bs" "1b_1mi.i, 1b_1mi.i")(final_presence_set "1b_0mm_bs" "1b_0mm.i, 1b_0mm.f, 1b_0mm.b")(final_presence_set "1b_1mm_bs" "1b_1mm.i, 1b_1mm.b")(final_presence_set "1b_0mf_bs" "1b_0mf.i, 1b_0mf.b")(final_presence_set "1b_1mf_bs" "1b_1mf.i, 1b_1mf.b")(final_presence_set "1b_0b_bs" "1b_0b.bb")(final_presence_set "1b_1b_bs" "1b_1b.bb")(final_presence_set "1b_0bb_bs" "1b_0bb.b")(final_presence_set "1b_1bb_bs" "1b_1bb.b")(final_presence_set "1b_0mb_bs" "1b_0mb.b")(final_presence_set "1b_1mb_bs" "1b_1mb.b")(exclusion_set "1b_0m_bs" "1b_0mi.i, 1b_0mm.i, 1b_0mm.f, 1b_0mf.i, 1b_0mb.b,\ 1b_0mi.b, 1b_0mf.b, 1b_0mm.b, 1b_0mlx., 1b_m0_stop")(exclusion_set "1b_1m_bs" "1b_1mi.i, 1b_1mm.i, 1b_1mf.i, 1b_1mb.b, 1b_1mi.b, 1b_1mf.b, 1b_1mm.b,\ 1b_1mlx., 1b_m1_stop")(exclusion_set "1b_0mi_bs" "1b_0mii., 1b_0mib., 1b_mi0_stop")(exclusion_set "1b_1mi_bs" "1b_1mii., 1b_1mib., 1b_mi1_stop")(exclusion_set "1b_0mm_bs" "1b_0mmi., 1b_0mmf., 1b_0mmb.")(exclusion_set "1b_1mm_bs" "1b_1mmi., 1b_1mmb.")(exclusion_set "1b_0mf_bs" "1b_0mfi., 1b_0mfb.")(exclusion_set "1b_1mf_bs" "1b_1mfi., 1b_1mfb.")(exclusion_set "1b_0b_bs" "1b_0bb.b")(exclusion_set "1b_1b_bs" "1b_1bb.b")(exclusion_set "1b_0bb_bs" "1b_0bbb.")(exclusion_set "1b_1bb_bs" "1b_1bbb.")(exclusion_set "1b_0mb_bs" "1b_0mbb.")(exclusion_set "1b_1mb_bs" "1b_1mbb.")(exclusion_set "1b_0m_bs, 1b_0mi_bs, 1b_0mm_bs, 1b_0mf_bs, 1b_0b_bs, 1b_0bb_bs, 1b_0mb_bs, 1b_1m_bs, 1b_1mi_bs, 1b_1mm_bs, 1b_1mf_bs, 1b_1b_bs, 1b_1bb_bs, 1b_1mb_bs" "1b_stop")(final_presence_set "1b_0mi.i, 1b_0mm.i, 1b_0mf.i, 1b_0mm.f, 1b_0mb.b,\ 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx." "1b_m_cont")(final_presence_set "1b_0mii., 1b_0mib." "1b_mi_cont")(final_presence_set "1b_0mmi., 1b_0mmf., 1b_0mmb." "1b_mm_cont")(final_presence_set "1b_0mfi., 1b_0mfb." "1b_mf_cont")(final_presence_set "1b_0bb.b" "1b_b_cont")(final_presence_set "1b_0bbb." "1b_bb_cont")(final_presence_set "1b_0mbb." "1b_mb_cont")(exclusion_set "1b_0m.ii, 1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\ 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx" "1b_m_cont, 1b_mi_cont, 1b_mm_cont, 1b_mf_cont,\ 1b_mb_cont, 1b_b_cont, 1b_bb_cont")(exclusion_set "1b_empty" "1b_m_cont,1b_mi_cont,1b_mm_cont,1b_mf_cont,\ 1b_mb_cont,1b_b_cont,1b_bb_cont");; For m;mi bundle(final_presence_set "1b_m0_stop" "1b_0m.mi")(final_presence_set "1b_0mm.i" "1b_0mmi_cont")(exclusion_set "1b_0mmi_cont" "1b_0m.ii, 1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\ 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx")(exclusion_set "1b_m0_stop" "1b_0mm.i")(final_presence_set "1b_m1_stop" "1b_1m.mi")(exclusion_set "1b_m1_stop" "1b_1mm.i")(final_presence_set "1b_m_stop" "1b_m0_stop, 1b_m1_stop");; For mi;i bundle(final_presence_set "1b_mi0_stop" "1b_0mi.i")(final_presence_set "1b_0mii." "1b_0mii_cont")(exclusion_set "1b_0mii_cont" "1b_0m.ii, 1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\ 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx")(exclusion_set "1b_mi0_stop" "1b_0mii.")(final_presence_set "1b_mi1_stop" "1b_1mi.i")(exclusion_set "1b_mi1_stop" "1b_1mii.")(final_presence_set "1b_mi_stop" "1b_mi0_stop, 1b_mi1_stop")(final_absence_set "1b_0m.ii,1b_0mi.i,1b_0mii.,1b_0m.mi,1b_0mm.i,1b_0mmi.,\ 1b_0m.fi,1b_0mf.i,1b_0mfi.,1b_0m.mf,1b_0mm.f,1b_0mmf.,\ 1b_0b.bb,1b_0bb.b,1b_0bbb.,1b_0m.bb,1b_0mb.b,1b_0mbb.,\ 1b_0m.ib,1b_0mi.b,1b_0mib.,1b_0m.mb,1b_0mm.b,1b_0mmb.,\ 1b_0m.fb,1b_0mf.b,1b_0mfb.,1b_0m.lx,1b_0mlx., \ 1b_1m.ii,1b_1mi.i,1b_1mii.,1b_1m.mi,1b_1mm.i,1b_1mmi.,\ 1b_1m.fi,1b_1mf.i,1b_1mfi.,\ 1b_1b.bb,1b_1bb.b,1b_1bbb.,1b_1m.bb,1b_1mb.b,1b_1mbb.,\ 1b_1m.ib,1b_1mi.b,1b_1mib.,1b_1m.mb,1b_1mm.b,1b_1mmb.,\ 1b_1m.fb,1b_1mf.b,1b_1mfb.,1b_1m.lx,1b_1mlx." "1b_m0_stop,1b_m1_stop,1b_mi0_stop,1b_mi1_stop")(define_reservation "1b_A" "1b_M|1b_I")(define_insn_reservation "1b_stop_bit" 0 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "stop_bit")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_stop|1b_m0_stop|1b_m1_stop|1b_mi0_stop|1b_mi1_stop")(define_insn_reservation "1b_br" 0 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "br")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_B")(define_insn_reservation "1b_scall" 0 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "scall")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_B")(define_insn_reservation "1b_fcmp" 2 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "fcmp")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F+1b_not_uf1")(define_insn_reservation "1b_fcvtfx" 7 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "fcvtfx")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F")(define_insn_reservation "1b_fld" 9 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "fld")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")(define_insn_reservation "1b_fldp" 9 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "fldp")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")(define_insn_reservation "1b_fmac" 5 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "fmac")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F")(define_insn_reservation "1b_fmisc" 5 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "fmisc")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F+1b_not_uf1")(define_insn_reservation "1b_frar_i" 13 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "frar_i")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I+1b_not_ui1")(define_insn_reservation "1b_frar_m" 6 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "frar_m")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M+1b_not_um1")(define_insn_reservation "1b_frbr" 2 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "frbr")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I+1b_not_ui1")(define_insn_reservation "1b_frfr" 2 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "frfr")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M+1b_not_um1")(define_insn_reservation "1b_frpr" 2 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "frpr")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I+1b_not_ui1")(define_insn_reservation "1b_ialu" 1 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "ialu")) (ne (symbol_ref "bundling_p && !ia64_produce_address_p (insn)") (const_int 0))) "1b_A")(define_insn_reservation "1b_ialu_addr" 1 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "ialu")) (eq (symbol_ref "bundling_p && ia64_produce_address_p (insn)") (const_int 1))) "1b_M")(define_insn_reservation "1b_icmp" 1 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "icmp")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A")(define_insn_reservation "1b_ilog" 1 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "ilog")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A")(define_insn_reservation "1b_mmalua" 2 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "mmalua")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A")(define_insn_reservation "1b_ishf" 1 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "ishf")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I+1b_not_ui1")(define_insn_reservation "1b_ld" 2 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "ld")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")(define_insn_reservation "1b_long_i" 1 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "long_i")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_L")(define_insn_reservation "1b_mmmul" 2 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "mmmul")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I+1b_not_ui1")(define_insn_reservation "1b_mmshf" 2 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "mmshf")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I")(define_insn_reservation "1b_mmshfi" 2 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "mmshfi")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I")(define_insn_reservation "1b_rse_m" 0 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "rse_m")) (ne (symbol_ref "bundling_p") (const_int 0))) "(1b_0m.ii|1b_0m.mi|1b_0m.fi|1b_0m.mf|1b_0b.bb|1b_0m.bb\ |1b_0m.ib|1b_0m.mb|1b_0m.fb|1b_0m.lx)+1_1+1b_um0")(define_insn_reservation "1b_sem" 0 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "sem")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M+1b_not_um1")(define_insn_reservation "1b_stf" 1 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "stf")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")(define_insn_reservation "1b_st" 1 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "st")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")(define_insn_reservation "1b_syst_m0" 0 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "syst_m0")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M+1b_not_um1")(define_insn_reservation "1b_syst_m" 0 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "syst_m")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")(define_insn_reservation "1b_tbit" 1 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "tbit")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I+1b_not_ui1")(define_insn_reservation "1b_toar_i" 0 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "toar_i")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I+1b_not_ui1")(define_insn_reservation "1b_toar_m" 5 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "toar_m")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M+1b_not_um1")(define_insn_reservation "1b_tobr" 1 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "tobr")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I+1b_not_ui1")(define_insn_reservation "1b_tofr" 9 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "tofr")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")(define_insn_reservation "1b_topr" 1 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "topr")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I+1b_not_ui1")(define_insn_reservation "1b_xmpy" 7 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "xmpy")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F")(define_insn_reservation "1b_xtd" 1 (and (and (eq_attr "cpu" "itanium") (eq_attr "itanium_class" "xtd")) (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I")(define_insn_reservation "1b_chk_s" 0 (and (and (eq_attr "cpu" "itanium") (eq_attr
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