itanium1.md

linux下编程用 编译软件

(define_bypass  3 "1_ld" "1_mmmul,1_mmshf")
(define_bypass  3 "1_ld" "1_ld"  "ia64_ld_address_bypass_p")
(define_bypass  3 "1_ld" "1_st"  "ia64_st_address_bypass_p")

;; Intel docs say only LD, ST, IALU, ILOG, ISHF consumers have latency 4,
;;      but HP engineers say any non-MM operation.
(define_bypass  4 "1_mmmul,1_mmshf,1_mmalua"
     "1_br,1_fcmp,1_fcvtfx,1_fld,1_fmac,1_fmisc,1_frar_i,1_frar_m,\
      1_frbr,1_frfr,1_frpr,1_ialu,1_icmp,1_ilog,1_ishf,1_ld,1_chk_s,\
      1_long_i,1_rse_m,1_sem,1_stf,1_st,1_syst_m0,1_syst_m,\
      1_tbit,1_toar_i,1_toar_m,1_tobr,1_tofr,1_topr,1_xmpy,1_xtd")

;; ??? how to describe that if scheduled < 4 cycle then latency is 10 cycles.
;; (define_bypass  10 "1_mmmul,1_mmshf" "1_ialu,1_ilog,1_ishf,1_st,1_ld")

(define_bypass  0 "1_tbit" "1_br,1_scall")

(define_bypass  8 "1_tofr"  "1_frfr,1_stf")
(define_bypass  7 "1_fmisc,1_fcvtfx,1_fmac,1_xmpy"  "1_frfr")
(define_bypass  8 "1_fmisc,1_fcvtfx,1_fmac,1_xmpy"  "1_stf")

;; We don't use here fcmp because scall may be predicated.
(define_bypass  0 "1_fcvtfx,1_fld,1_fmac,1_fmisc,1_frar_i,1_frar_m,\
                   1_frbr,1_frfr,1_frpr,1_ialu,1_ialu_addr,1_ilog,1_ishf,\
	           1_ld,1_long_i,1_mmalua,1_mmmul,1_mmshf,1_mmshfi,1_toar_m,\
		   1_tofr,1_xmpy,1_xtd" "1_scall")

(define_bypass  0 "1_unknown,1_ignore,1_stop_bit,1_br,1_fcmp,1_fcvtfx,\
                   1_fld,1_fmac,1_fmisc,1_frar_i,1_frar_m,1_frbr,1_frfr,\
                   1_frpr,1_ialu,1_ialu_addr,1_icmp,1_ilog,1_ishf,1_ld,\
                   1_chk_s,1_long_i,1_mmalua,1_mmmul,1_mmshf,1_mmshfi,1_nop,\
                   1_nop_b,1_nop_f,1_nop_i,1_nop_m,1_nop_x,1_rse_m,1_scall,\
                   1_sem,1_stf,1_st,1_syst_m0,1_syst_m,1_tbit,1_toar_i,\
                   1_toar_m,1_tobr,1_tofr,1_topr,1_xmpy,1_xtd,1_lfetch"
                  "1_ignore")


;; Bundling

(define_automaton "oneb")

;; Pseudo units for quicker searching for position in two packet window.  */
(define_query_cpu_unit "1_1,1_2,1_3,1_4,1_5,1_6" "oneb")

;;   All possible combinations of bundles/syllables
(define_cpu_unit
   "1b_0m.ii, 1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\
    1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx" "oneb")
(define_cpu_unit
   "1b_0mi.i, 1b_0mm.i, 1b_0mf.i, 1b_0mm.f, 1b_0bb.b, 1b_0mb.b,\
    1b_0mi.b, 1b_0mm.b, 1b_0mf.b" "oneb")
(define_query_cpu_unit
   "1b_0mii., 1b_0mmi., 1b_0mfi., 1b_0mmf., 1b_0bbb., 1b_0mbb.,\
    1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx." "oneb")

(define_cpu_unit "1b_1m.ii, 1b_1m.mi, 1b_1m.fi, 1b_1b.bb, 1b_1m.bb,\
                  1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx" "oneb")
(define_cpu_unit "1b_1mi.i, 1b_1mm.i, 1b_1mf.i, 1b_1bb.b, 1b_1mb.b,\
                  1b_1mi.b, 1b_1mm.b, 1b_1mf.b" "oneb")
(define_query_cpu_unit "1b_1mii., 1b_1mmi., 1b_1mfi., 1b_1bbb., 1b_1mbb.,\
                        1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx." "oneb")

;; Slot 1
(exclusion_set "1b_0m.ii"
   "1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\
    1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx")
(exclusion_set "1b_0m.mi"
   "1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb, 1b_0m.ib,\
    1b_0m.mb, 1b_0m.fb, 1b_0m.lx")
(exclusion_set "1b_0m.fi"
   "1b_0m.mf, 1b_0b.bb, 1b_0m.bb, 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx")
(exclusion_set "1b_0m.mf"
   "1b_0b.bb, 1b_0m.bb, 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx")
(exclusion_set "1b_0b.bb" "1b_0m.bb, 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx")
(exclusion_set "1b_0m.bb" "1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx")
(exclusion_set "1b_0m.ib" "1b_0m.mb, 1b_0m.fb, 1b_0m.lx")
(exclusion_set "1b_0m.mb" "1b_0m.fb, 1b_0m.lx")
(exclusion_set "1b_0m.fb" "1b_0m.lx")

;; Slot 2
(exclusion_set "1b_0mi.i"
   "1b_0mm.i, 1b_0mf.i, 1b_0mm.f, 1b_0bb.b, 1b_0mb.b,\
    1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.")
(exclusion_set "1b_0mm.i"
   "1b_0mf.i, 1b_0mm.f, 1b_0bb.b, 1b_0mb.b,\
    1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.")
(exclusion_set "1b_0mf.i"
   "1b_0mm.f, 1b_0bb.b, 1b_0mb.b, 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.")
(exclusion_set "1b_0mm.f"
   "1b_0bb.b, 1b_0mb.b, 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.")
(exclusion_set "1b_0bb.b" "1b_0mb.b, 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.")
(exclusion_set "1b_0mb.b" "1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.")
(exclusion_set "1b_0mi.b" "1b_0mm.b, 1b_0mf.b, 1b_0mlx.")
(exclusion_set "1b_0mm.b" "1b_0mf.b, 1b_0mlx.")
(exclusion_set "1b_0mf.b" "1b_0mlx.")

;; Slot 3
(exclusion_set "1b_0mii."
   "1b_0mmi., 1b_0mfi., 1b_0mmf., 1b_0bbb., 1b_0mbb.,\
    1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.")
(exclusion_set "1b_0mmi."
   "1b_0mfi., 1b_0mmf., 1b_0bbb., 1b_0mbb.,\
    1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.")
(exclusion_set "1b_0mfi."
   "1b_0mmf., 1b_0bbb., 1b_0mbb., 1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.")
(exclusion_set "1b_0mmf."
   "1b_0bbb., 1b_0mbb., 1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.")
(exclusion_set "1b_0bbb." "1b_0mbb., 1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.")
(exclusion_set "1b_0mbb." "1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.")
(exclusion_set "1b_0mib." "1b_0mmb., 1b_0mfb., 1b_0mlx.")
(exclusion_set "1b_0mmb." "1b_0mfb., 1b_0mlx.")
(exclusion_set "1b_0mfb." "1b_0mlx.")

;; Slot 4
(exclusion_set "1b_1m.ii"
   "1b_1m.mi, 1b_1m.fi, 1b_1b.bb, 1b_1m.bb,\
    1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx")
(exclusion_set "1b_1m.mi"
   "1b_1m.fi, 1b_1b.bb, 1b_1m.bb, 1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx")
(exclusion_set "1b_1m.fi"
   "1b_1b.bb, 1b_1m.bb, 1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx")
(exclusion_set "1b_1b.bb" "1b_1m.bb, 1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx")
(exclusion_set "1b_1m.bb" "1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx")
(exclusion_set "1b_1m.ib" "1b_1m.mb, 1b_1m.fb, 1b_1m.lx")
(exclusion_set "1b_1m.mb" "1b_1m.fb, 1b_1m.lx")
(exclusion_set "1b_1m.fb" "1b_1m.lx")

;; Slot 5
(exclusion_set "1b_1mi.i"
   "1b_1mm.i, 1b_1mf.i, 1b_1bb.b, 1b_1mb.b,\
    1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.")
(exclusion_set "1b_1mm.i"
   "1b_1mf.i, 1b_1bb.b, 1b_1mb.b, 1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.")
(exclusion_set "1b_1mf.i"
   "1b_1bb.b, 1b_1mb.b, 1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.")
(exclusion_set "1b_1bb.b" "1b_1mb.b, 1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.")
(exclusion_set "1b_1mb.b" "1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.")
(exclusion_set "1b_1mi.b" "1b_1mm.b, 1b_1mf.b, 1b_1mlx.")
(exclusion_set "1b_1mm.b" "1b_1mf.b, 1b_1mlx.")
(exclusion_set "1b_1mf.b" "1b_1mlx.")

;; Slot 6
(exclusion_set "1b_1mii."
   "1b_1mmi., 1b_1mfi., 1b_1bbb., 1b_1mbb.,\
    1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.")
(exclusion_set "1b_1mmi."
   "1b_1mfi., 1b_1bbb., 1b_1mbb., 1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.")
(exclusion_set "1b_1mfi."
   "1b_1bbb., 1b_1mbb., 1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.")
(exclusion_set "1b_1bbb." "1b_1mbb., 1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.")
(exclusion_set "1b_1mbb." "1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.")
(exclusion_set "1b_1mib." "1b_1mmb., 1b_1mfb., 1b_1mlx.")
(exclusion_set "1b_1mmb." "1b_1mfb., 1b_1mlx.")
(exclusion_set "1b_1mfb." "1b_1mlx.")

(final_presence_set "1b_0mi.i" "1b_0m.ii")
(final_presence_set "1b_0mii." "1b_0mi.i")
(final_presence_set "1b_1mi.i" "1b_1m.ii")
(final_presence_set "1b_1mii." "1b_1mi.i")

(final_presence_set "1b_0mm.i" "1b_0m.mi")
(final_presence_set "1b_0mmi." "1b_0mm.i")
(final_presence_set "1b_1mm.i" "1b_1m.mi")
(final_presence_set "1b_1mmi." "1b_1mm.i")

(final_presence_set "1b_0mf.i" "1b_0m.fi")
(final_presence_set "1b_0mfi." "1b_0mf.i")
(final_presence_set "1b_1mf.i" "1b_1m.fi")
(final_presence_set "1b_1mfi." "1b_1mf.i")

(final_presence_set "1b_0mm.f" "1b_0m.mf")
(final_presence_set "1b_0mmf." "1b_0mm.f")

(final_presence_set "1b_0bb.b" "1b_0b.bb")
(final_presence_set "1b_0bbb." "1b_0bb.b")
(final_presence_set "1b_1bb.b" "1b_1b.bb")
(final_presence_set "1b_1bbb." "1b_1bb.b")

(final_presence_set "1b_0mb.b" "1b_0m.bb")
(final_presence_set "1b_0mbb." "1b_0mb.b")
(final_presence_set "1b_1mb.b" "1b_1m.bb")
(final_presence_set "1b_1mbb." "1b_1mb.b")

(final_presence_set "1b_0mi.b" "1b_0m.ib")
(final_presence_set "1b_0mib." "1b_0mi.b")
(final_presence_set "1b_1mi.b" "1b_1m.ib")
(final_presence_set "1b_1mib." "1b_1mi.b")

(final_presence_set "1b_0mm.b" "1b_0m.mb")
(final_presence_set "1b_0mmb." "1b_0mm.b")
(final_presence_set "1b_1mm.b" "1b_1m.mb")
(final_presence_set "1b_1mmb." "1b_1mm.b")

(final_presence_set "1b_0mf.b" "1b_0m.fb")
(final_presence_set "1b_0mfb." "1b_0mf.b")
(final_presence_set "1b_1mf.b" "1b_1m.fb")
(final_presence_set "1b_1mfb." "1b_1mf.b")

(final_presence_set "1b_0mlx." "1b_0m.lx")
(final_presence_set "1b_1mlx." "1b_1m.lx")

(final_presence_set
   "1b_1m.ii,1b_1m.mi,1b_1m.fi,1b_1b.bb,1b_1m.bb,\
    1b_1m.ib,1b_1m.mb,1b_1m.fb,1b_1m.lx"
   "1b_0mii.,1b_0mmi.,1b_0mfi.,1b_0mmf.,1b_0bbb.,1b_0mbb.,\
    1b_0mib.,1b_0mmb.,1b_0mfb.,1b_0mlx.")

;;  Microarchitecture units:
(define_cpu_unit
   "1b_um0, 1b_um1, 1b_ui0, 1b_ui1, 1b_uf0, 1b_uf1, 1b_ub0, 1b_ub1, 1b_ub2,\
    1b_unb0, 1b_unb1, 1b_unb2" "oneb")

(exclusion_set "1b_ub0" "1b_unb0")
(exclusion_set "1b_ub1" "1b_unb1")
(exclusion_set "1b_ub2" "1b_unb2")

;; The following rules are used to decrease number of alternatives.
;; They are consequences of Itanium microarchitecture.  They also
;; describe the following rules mentioned in Itanium
;; microarchitecture: rules mentioned in Itanium microarchitecture:
;; o "MMF: Always splits issue before the first M and after F regardless
;;   of surrounding bundles and stops".
;; o "BBB/MBB: Always splits issue after either of these bundles".
;; o "MIB BBB: Split issue after the first bundle in this pair".

(exclusion_set "1b_0m.mf,1b_0mm.f,1b_0mmf."
   "1b_1m.ii,1b_1m.mi,1b_1m.fi,1b_1b.bb,1b_1m.bb,\
    1b_1m.ib,1b_1m.mb,1b_1m.fb,1b_1m.lx")
(exclusion_set "1b_0b.bb,1b_0bb.b,1b_0bbb.,1b_0m.bb,1b_0mb.b,1b_0mbb."
   "1b_1m.ii,1b_1m.mi,1b_1m.fi,1b_1b.bb,1b_1m.bb,\
    1b_1m.ib,1b_1m.mb,1b_1m.fb,1b_1m.lx")
(exclusion_set "1b_0m.ib,1b_0mi.b,1b_0mib." "1b_1b.bb")

;;  For exceptions of M, I, B, F insns:
(define_cpu_unit "1b_not_um1, 1b_not_ui1, 1b_not_uf1" "oneb")

(final_absence_set "1b_not_um1"  "1b_um1")
(final_absence_set "1b_not_ui1"  "1b_ui1")
(final_absence_set "1b_not_uf1"  "1b_uf1")

;;; "MIB/MFB/MMB: Splits issue after any of these bundles unless the
;;; B-slot contains a nop.b or a brp instruction".
;;;   "The B in an MIB/MFB/MMB bundle disperses to B0 if it is a brp or
;;; nop.b, otherwise it disperses to B2".
(final_absence_set
   "1b_1m.ii, 1b_1m.mi, 1b_1m.fi, 1b_1b.bb, 1b_1m.bb,\
    1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx"
   "1b_0mib. 1b_ub2, 1b_0mfb. 1b_ub2, 1b_0mmb. 1b_ub2")

;; This is necessary to start new processor cycle when we meet stop bit.
(define_cpu_unit "1b_stop" "oneb")
(final_absence_set
   "1b_0m.ii,1b_0mi.i,1b_0mii.,1b_0m.mi,1b_0mm.i,1b_0mmi.,\
    1b_0m.fi,1b_0mf.i,1b_0mfi.,\
    1b_0m.mf,1b_0mm.f,1b_0mmf.,1b_0b.bb,1b_0bb.b,1b_0bbb.,\
    1b_0m.bb,1b_0mb.b,1b_0mbb.,\
    1b_0m.ib,1b_0mi.b,1b_0mib.,1b_0m.mb,1b_0mm.b,1b_0mmb.,\
    1b_0m.fb,1b_0mf.b,1b_0mfb.,1b_0m.lx,1b_0mlx., \
    1b_1m.ii,1b_1mi.i,1b_1mii.,1b_1m.mi,1b_1mm.i,1b_1mmi.,\
    1b_1m.fi,1b_1mf.i,1b_1mfi.,\
    1b_1b.bb,1b_1bb.b,1b_1bbb.,1b_1m.bb,1b_1mb.b,1b_1mbb.,\
    1b_1m.ib,1b_1mi.b,1b_1mib.,\
    1b_1m.mb,1b_1mm.b,1b_1mmb.,1b_1m.fb,1b_1mf.b,1b_1mfb.,1b_1m.lx,1b_1mlx."
   "1b_stop")

;; M and I instruction is dispersed to the lowest numbered M or I unit
;; not already in use.  An I slot in the 3rd position of 2nd bundle is
;; always dispersed to I1
(final_presence_set "1b_um1" "1b_um0")
(final_presence_set "1b_ui1" "1b_ui0, 1b_1mii., 1b_1mmi., 1b_1mfi.")

;; Insns

;; M and I instruction is dispersed to the lowest numbered M or I unit
;; not already in use.  An I slot in the 3rd position of 2nd bundle is
;; always dispersed to I1
(define_reservation "1b_M"
  "1b_0m.ii+1_1+1b_um0|1b_0m.mi+1_1+1b_um0|1b_0mm.i+1_2+(1b_um0|1b_um1)\
   |1b_0m.fi+1_1+1b_um0|1b_0m.mf+1_1+1b_um0|1b_0mm.f+1_2+1b_um1\
   |1b_0m.bb+1_1+1b_um0|1b_0m.ib+1_1+1b_um0|1b_0m.mb+1_1+1b_um0\
   |1b_0mm.b+1_2+1b_um1|1b_0m.fb+1_1+1b_um0|1b_0m.lx+1_1+1b_um0\
   |1b_1mm.i+1_5+1b_um1|1b_1mm.b+1_5+1b_um1\
   |(1b_1m.ii+1_4|1b_1m.mi+1_4|1b_1m.fi+1_4|1b_1m.bb+1_4|1b_1m.ib+1_4\
     |1b_1m.mb+1_4|1b_1m.fb+1_4|1b_1m.lx+1_4)\
    +(1b_um0|1b_um1)")

;;  Exceptions for dispersal rules.
;; "An I slot in the 3rd position of 2nd bundle is always dispersed to I1".
(define_reservation "1b_I"
  "1b_0mi.i+1_2+1b_ui0|1b_0mii.+1_3+(1b_ui0|1b_ui1)|1b_0mmi.+1_3+1b_ui0\
   |1b_0mfi.+1_3+1b_ui0|1b_0mi.b+1_2+1b_ui0\
   |(1b_1mi.i+1_5|1b_1mi.b+1_5)+(1b_ui0|1b_ui1)\
   |1b_1mii.+1_6+1b_ui1|1b_1mmi.+1_6+1b_ui1|1b_1mfi.+1_6+1b_ui1")

;; "An F slot in the 1st bundle disperses to F0".
;; "An F slot in the 2st bundle disperses to F1".
(define_reservation "1b_F"
   "1b_0mf.i+1_2+1b_uf0|1b_0mmf.+1_3+1b_uf0|1b_0mf.b+1_2+1b_uf0\
    |1b_1mf.i+1_5+1b_uf1|1b_1mf.b+1_5+1b_uf1")

;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B
;;; unit. That is, a B slot in 1st position is dispersed to B0.  In the
;;; 2nd position it is dispersed to B2".
(define_reservation "1b_NB"
    "1b_0b.bb+1_1+1b_unb0|1b_0bb.b+1_2+1b_unb1|1b_0bbb.+1_3+1b_unb2\
     |1b_0mb.b+1_2+1b_unb1|1b_0mbb.+1_3+1b_unb2\
     |1b_0mib.+1_3+1b_unb0|1b_0mmb.+1_3+1b_unb0|1b_0mfb.+1_3+1b_unb0\
     |1b_1b.bb+1_4+1b_unb0|1b_1bb.b+1_5+1b_unb1\
     |1b_1bbb.+1_6+1b_unb2|1b_1mb.b+1_5+1b_unb1|1b_1mbb.+1_6+1b_unb2\
     |1b_1mib.+1_6+1b_unb0|1b_1mmb.+1_6+1b_unb0|1b_1mfb.+1_6+1b_unb0")

(define_reservation "1b_B"
   "1b_0b.bb+1_1+1b_ub0|1b_0bb.b+1_2+1b_ub1|1b_0bbb.+1_3+1b_ub2\
    |1b_0mb.b+1_2+1b_ub1|1b_0mbb.+1_3+1b_ub2|1b_0mib.+1_3+1b_ub2\
    |1b_0mfb.+1_3+1b_ub2|1b_1b.bb+1_4+1b_ub0|1b_1bb.b+1_5+1b_ub1\