itanium1.md

linux下编程用 编译软件

  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "rse_m"))
       (eq (symbol_ref "bundling_p") (const_int 0)))
  "(1_0m.ii|1_0m.mi|1_0m.fi|1_0m.mf|1_0b.bb|1_0m.bb\
    |1_0m.ib|1_0m.mb|1_0m.fb|1_0m.lx)+1_um0")
(define_insn_reservation "1_sem"     0
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "sem"))
       (eq (symbol_ref "bundling_p") (const_int 0)))
  "1_M+1_not_um1")
(define_insn_reservation "1_stf"     1
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "stf"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_st"      1
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "st"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_syst_m0" 0
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "syst_m0"))
       (eq (symbol_ref "bundling_p") (const_int 0)))
  "1_M+1_not_um1")
(define_insn_reservation "1_syst_m"  0
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "syst_m"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_tbit"    1
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "tbit"))
       (eq (symbol_ref "bundling_p") (const_int 0)))
  "1_I+1_not_ui1")

;; There is only ony insn `mov ar.pfs =' for toar_i:
(define_insn_reservation "1_toar_i"  0
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "toar_i"))
       (eq (symbol_ref "bundling_p") (const_int 0)))
  "1_I+1_not_ui1")
;; There are only ony 2 insns `mov ar.ccv =' and `mov ar.unat =' for toar_m:
(define_insn_reservation "1_toar_m"  5
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "toar_m"))
       (eq (symbol_ref "bundling_p") (const_int 0)))
  "1_M+1_not_um1")
(define_insn_reservation "1_tobr"    1
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "tobr"))
       (eq (symbol_ref "bundling_p") (const_int 0)))
  "1_I+1_not_ui1")
(define_insn_reservation "1_tofr"    9
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "tofr"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_topr"    1
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "topr"))
       (eq (symbol_ref "bundling_p") (const_int 0)))
  "1_I+1_not_ui1")
(define_insn_reservation "1_xmpy"    7
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "xmpy"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_F")
(define_insn_reservation "1_xtd"     1
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "xtd"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_I")

(define_insn_reservation "1_chk_s"   0
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "chk_s"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_A")
(define_insn_reservation "1_lfetch"  0
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "lfetch"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")

(define_insn_reservation "1_nop_m"   0
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "nop_m"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_M0")
(define_insn_reservation "1_nop_b"   0
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "nop_b"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_NB")
(define_insn_reservation "1_nop_i"   0
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "nop_i"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_I0")
(define_insn_reservation "1_nop_f"   0
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "nop_f"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_F0")
(define_insn_reservation "1_nop_x"   0
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "nop_x"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_L0")

;; We assume that there is no insn issued on the same cycle as unknown insn.
(define_cpu_unit "1_empty" "one")
(exclusion_set "1_empty"
    "1_0m.ii,1_0m.mi,1_0m.fi,1_0m.mf,1_0b.bb,1_0m.bb,1_0m.ib,1_0m.mb,1_0m.fb,\
     1_0m.lx")

(define_insn_reservation "1_unknown" 1
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "unknown"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_empty")

(define_insn_reservation "1_nop" 1
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "nop"))
       (eq (symbol_ref "bundling_p") (const_int 0)))
  "1_M0|1_NB|1_I0|1_F0")

(define_insn_reservation "1_ignore" 0
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "ignore"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "nothing")


(define_cpu_unit
   "1_0m_bs, 1_0mi_bs, 1_0mm_bs, 1_0mf_bs, 1_0b_bs, 1_0bb_bs, 1_0mb_bs"
   "one")
(define_cpu_unit
   "1_1m_bs, 1_1mi_bs, 1_1mm_bs, 1_1mf_bs, 1_1b_bs, 1_1bb_bs, 1_1mb_bs"
   "one")

(define_cpu_unit "1_m_cont, 1_mi_cont, 1_mm_cont, 1_mf_cont, 1_mb_cont,\
	          1_b_cont, 1_bb_cont" "one")

;; For stop in the middle of the bundles.
(define_cpu_unit "1_m_stop, 1_m0_stop, 1_m1_stop, 1_0mmi_cont" "one")
(define_cpu_unit "1_mi_stop, 1_mi0_stop, 1_mi1_stop, 1_0mii_cont" "one")

(final_presence_set "1_0m_bs"
   "1_0m.ii, 1_0m.mi, 1_0m.mf, 1_0m.fi, 1_0m.bb,\
    1_0m.ib, 1_0m.fb, 1_0m.mb, 1_0m.lx")
(final_presence_set "1_1m_bs"
   "1_1m.ii, 1_1m.mi, 1_1m.fi, 1_1m.bb, 1_1m.ib, 1_1m.fb, 1_1m.mb,\
    1_1m.lx")
(final_presence_set "1_0mi_bs"  "1_0mi.i, 1_0mi.i")
(final_presence_set "1_1mi_bs"  "1_1mi.i, 1_1mi.i")
(final_presence_set "1_0mm_bs"  "1_0mm.i, 1_0mm.f, 1_0mm.b")
(final_presence_set "1_1mm_bs"  "1_1mm.i, 1_1mm.b")
(final_presence_set "1_0mf_bs"  "1_0mf.i, 1_0mf.b")
(final_presence_set "1_1mf_bs"  "1_1mf.i, 1_1mf.b")
(final_presence_set "1_0b_bs"  "1_0b.bb")
(final_presence_set "1_1b_bs"  "1_1b.bb")
(final_presence_set "1_0bb_bs"  "1_0bb.b")
(final_presence_set "1_1bb_bs"  "1_1bb.b")
(final_presence_set "1_0mb_bs"  "1_0mb.b")
(final_presence_set "1_1mb_bs"  "1_1mb.b")

(exclusion_set "1_0m_bs"
   "1_0mi.i, 1_0mm.i, 1_0mm.f, 1_0mf.i, 1_0mb.b,\
    1_0mi.b, 1_0mf.b, 1_0mm.b, 1_0mlx., 1_m0_stop")
(exclusion_set "1_1m_bs"
   "1_1mi.i, 1_1mm.i, 1_1mf.i, 1_1mb.b, 1_1mi.b, 1_1mf.b, 1_1mm.b,\
    1_1mlx., 1_m1_stop")
(exclusion_set "1_0mi_bs"  "1_0mii., 1_0mib., 1_mi0_stop")
(exclusion_set "1_1mi_bs"  "1_1mii., 1_1mib., 1_mi1_stop")
(exclusion_set "1_0mm_bs"  "1_0mmi., 1_0mmf., 1_0mmb.")
(exclusion_set "1_1mm_bs"  "1_1mmi., 1_1mmb.")
(exclusion_set "1_0mf_bs"  "1_0mfi., 1_0mfb.")
(exclusion_set "1_1mf_bs"  "1_1mfi., 1_1mfb.")
(exclusion_set "1_0b_bs"  "1_0bb.b")
(exclusion_set "1_1b_bs"  "1_1bb.b")
(exclusion_set "1_0bb_bs"  "1_0bbb.")
(exclusion_set "1_1bb_bs"  "1_1bbb.")
(exclusion_set "1_0mb_bs"  "1_0mbb.")
(exclusion_set "1_1mb_bs"  "1_1mbb.")

(exclusion_set
   "1_0m_bs, 1_0mi_bs, 1_0mm_bs, 1_0mf_bs, 1_0b_bs, 1_0bb_bs, 1_0mb_bs,
    1_1m_bs, 1_1mi_bs, 1_1mm_bs, 1_1mf_bs, 1_1b_bs, 1_1bb_bs, 1_1mb_bs"
   "1_stop")

(final_presence_set
   "1_0mi.i, 1_0mm.i, 1_0mf.i, 1_0mm.f, 1_0mb.b,\
    1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx."
   "1_m_cont")
(final_presence_set "1_0mii., 1_0mib." "1_mi_cont")
(final_presence_set "1_0mmi., 1_0mmf., 1_0mmb." "1_mm_cont")
(final_presence_set "1_0mfi., 1_0mfb." "1_mf_cont")
(final_presence_set "1_0bb.b" "1_b_cont")
(final_presence_set "1_0bbb." "1_bb_cont")
(final_presence_set "1_0mbb." "1_mb_cont")

(exclusion_set
   "1_0m.ii, 1_0m.mi, 1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb,\
    1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx"
   "1_m_cont, 1_mi_cont, 1_mm_cont, 1_mf_cont,\
    1_mb_cont, 1_b_cont, 1_bb_cont")

(exclusion_set "1_empty"
               "1_m_cont,1_mi_cont,1_mm_cont,1_mf_cont,\
                1_mb_cont,1_b_cont,1_bb_cont")

;; For m;mi bundle
(final_presence_set "1_m0_stop" "1_0m.mi")
(final_presence_set "1_0mm.i" "1_0mmi_cont")
(exclusion_set "1_0mmi_cont"
   "1_0m.ii, 1_0m.mi, 1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb,\
    1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx")
(exclusion_set "1_m0_stop" "1_0mm.i")
(final_presence_set "1_m1_stop" "1_1m.mi")
(exclusion_set "1_m1_stop" "1_1mm.i")
(final_presence_set "1_m_stop" "1_m0_stop, 1_m1_stop")

;; For mi;i bundle
(final_presence_set "1_mi0_stop" "1_0mi.i")
(final_presence_set "1_0mii." "1_0mii_cont")
(exclusion_set "1_0mii_cont"
   "1_0m.ii, 1_0m.mi, 1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb,\
    1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx")
(exclusion_set "1_mi0_stop" "1_0mii.")
(final_presence_set "1_mi1_stop" "1_1mi.i")
(exclusion_set "1_mi1_stop" "1_1mii.")
(final_presence_set "1_mi_stop" "1_mi0_stop, 1_mi1_stop")

(final_absence_set
   "1_0m.ii,1_0mi.i,1_0mii.,1_0m.mi,1_0mm.i,1_0mmi.,1_0m.fi,1_0mf.i,1_0mfi.,\
    1_0m.mf,1_0mm.f,1_0mmf.,1_0b.bb,1_0bb.b,1_0bbb.,1_0m.bb,1_0mb.b,1_0mbb.,\
    1_0m.ib,1_0mi.b,1_0mib.,1_0m.mb,1_0mm.b,1_0mmb.,1_0m.fb,1_0mf.b,1_0mfb.,\
    1_0m.lx,1_0mlx., \
    1_1m.ii,1_1mi.i,1_1mii.,1_1m.mi,1_1mm.i,1_1mmi.,1_1m.fi,1_1mf.i,1_1mfi.,\
    1_1b.bb,1_1bb.b,1_1bbb.,1_1m.bb,1_1mb.b,1_1mbb.,\
    1_1m.ib,1_1mi.b,1_1mib.,1_1m.mb,1_1mm.b,1_1mmb.,1_1m.fb,1_1mf.b,1_1mfb.,\
    1_1m.lx,1_1mlx."
   "1_m0_stop,1_m1_stop,1_mi0_stop,1_mi1_stop")

(define_cpu_unit "1_m_cont_only, 1_b_cont_only" "one")
(define_cpu_unit "1_mi_cont_only, 1_mm_cont_only, 1_mf_cont_only" "one")
(define_cpu_unit "1_mb_cont_only, 1_bb_cont_only" "one")

(final_presence_set "1_m_cont_only" "1_m_cont")
(exclusion_set "1_m_cont_only"
  "1_0mi.i, 1_0mm.i, 1_0mf.i, 1_0mm.f, 1_0mb.b,\
   1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.")

(final_presence_set "1_b_cont_only" "1_b_cont")
(exclusion_set "1_b_cont_only"  "1_0bb.b")

(final_presence_set "1_mi_cont_only" "1_mi_cont")
(exclusion_set "1_mi_cont_only" "1_0mii., 1_0mib.")

(final_presence_set "1_mm_cont_only" "1_mm_cont")
(exclusion_set "1_mm_cont_only" "1_0mmi., 1_0mmf., 1_0mmb.")

(final_presence_set "1_mf_cont_only" "1_mf_cont")
(exclusion_set "1_mf_cont_only" "1_0mfi., 1_0mfb.")

(final_presence_set "1_mb_cont_only" "1_mb_cont")
(exclusion_set "1_mb_cont_only" "1_0mbb.")

(final_presence_set "1_bb_cont_only" "1_bb_cont")
(exclusion_set "1_bb_cont_only" "1_0bbb.")

(define_insn_reservation "1_pre_cycle" 0
   (and (and (eq_attr "cpu" "itanium")
             (eq_attr "itanium_class" "pre_cycle"))
        (eq (symbol_ref "bundling_p") (const_int 0)))
                         "(1_0m_bs, 1_m_cont)                     \
                          | (1_0mi_bs, (1_mi_cont|nothing))       \
                          | (1_0mm_bs, 1_mm_cont)                 \
                          | (1_0mf_bs, (1_mf_cont|nothing))       \
                          | (1_0b_bs, (1_b_cont|nothing))         \
                          | (1_0bb_bs, (1_bb_cont|nothing))       \
                          | (1_0mb_bs, (1_mb_cont|nothing))       \
                          | (1_1m_bs, 1_m_cont)                   \
                          | (1_1mi_bs, (1_mi_cont|nothing))       \
                          | (1_1mm_bs, 1_mm_cont)                 \
                          | (1_1mf_bs, (1_mf_cont|nothing))       \
                          | (1_1b_bs, (1_b_cont|nothing))         \
                          | (1_1bb_bs, (1_bb_cont|nothing))       \
                          | (1_1mb_bs, (1_mb_cont|nothing))       \
                          | (1_m_cont_only, (1_m_cont|nothing))   \
                          | (1_b_cont_only,  (1_b_cont|nothing))  \
                          | (1_mi_cont_only, (1_mi_cont|nothing)) \
                          | (1_mm_cont_only, (1_mm_cont|nothing)) \
                          | (1_mf_cont_only, (1_mf_cont|nothing)) \
                          | (1_mb_cont_only, (1_mb_cont|nothing)) \
                          | (1_bb_cont_only, (1_bb_cont|nothing)) \
                          | (1_m_stop, (1_0mmi_cont|nothing))     \
                          | (1_mi_stop, (1_0mii_cont|nothing))")

;; Bypasses:
(define_bypass  1 "1_fcmp" "1_br,1_scall")
;; ??? I found 7 cycle delay for 1_fmac -> 1_fcmp for Itanium1
(define_bypass  7 "1_fmac" "1_fmisc,1_fcvtfx,1_xmpy,1_fcmp")

;; ???
(define_bypass  3 "1_frbr" "1_mmmul,1_mmshf")
(define_bypass 14 "1_frar_i" "1_mmmul,1_mmshf")
(define_bypass  7 "1_frar_m" "1_mmmul,1_mmshf")

;; ????
;; There is only one insn `mov ar.pfs =' for toar_i.
(define_bypass  0 "1_tobr,1_topr,1_toar_i" "1_br,1_scall")

(define_bypass  3 "1_ialu,1_ialu_addr" "1_mmmul,1_mmshf,1_mmalua")
;; ??? howto describe ialu for I slot only.  We use ialu_addr for that
;;(define_bypass  2 "1_ialu" "1_ld"  "ia64_ld_address_bypass_p")
;; ??? howto describe ialu st/address for I slot only.  We use ialu_addr
;;   for that.
;;(define_bypass  2 "1_ialu" "1_st"  "ia64_st_address_bypass_p")

(define_bypass  0 "1_icmp" "1_br,1_scall")

(define_bypass  3 "1_ilog" "1_mmmul,1_mmshf")

(define_bypass  2 "1_ilog,1_xtd" "1_ld"  "ia64_ld_address_bypass_p")
(define_bypass  2 "1_ilog,1_xtd" "1_st"  "ia64_st_address_bypass_p")