itanium1.md

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(final_presence_set "1_0bbb." "1_0bb.b")
(final_presence_set "1_1bb.b" "1_1b.bb")
(final_presence_set "1_1bbb." "1_1bb.b")

(final_presence_set "1_0mb.b" "1_0m.bb")
(final_presence_set "1_0mbb." "1_0mb.b")
(final_presence_set "1_1mb.b" "1_1m.bb")
(final_presence_set "1_1mbb." "1_1mb.b")

(final_presence_set "1_0mi.b" "1_0m.ib")
(final_presence_set "1_0mib." "1_0mi.b")
(final_presence_set "1_1mi.b" "1_1m.ib")
(final_presence_set "1_1mib." "1_1mi.b")

(final_presence_set "1_0mm.b" "1_0m.mb")
(final_presence_set "1_0mmb." "1_0mm.b")
(final_presence_set "1_1mm.b" "1_1m.mb")
(final_presence_set "1_1mmb." "1_1mm.b")

(final_presence_set "1_0mf.b" "1_0m.fb")
(final_presence_set "1_0mfb." "1_0mf.b")
(final_presence_set "1_1mf.b" "1_1m.fb")
(final_presence_set "1_1mfb." "1_1mf.b")

(final_presence_set "1_0mlx." "1_0m.lx")
(final_presence_set "1_1mlx." "1_1m.lx")

(final_presence_set
   "1_1m.ii,1_1m.mi,1_1m.fi,1_1b.bb,1_1m.bb,1_1m.ib,1_1m.mb,1_1m.fb,1_1m.lx"
   "1_0mii.,1_0mmi.,1_0mfi.,1_0mmf.,1_0bbb.,1_0mbb.,1_0mib.,1_0mmb.,1_0mfb.,\
    1_0mlx.")

;;  Microarchitecture units:
(define_cpu_unit
   "1_um0, 1_um1, 1_ui0, 1_ui1, 1_uf0, 1_uf1, 1_ub0, 1_ub1, 1_ub2,\
    1_unb0, 1_unb1, 1_unb2" "one")

(exclusion_set "1_ub0" "1_unb0")
(exclusion_set "1_ub1" "1_unb1")
(exclusion_set "1_ub2" "1_unb2")

;; The following rules are used to decrease number of alternatives.
;; They are consequences of Itanium microarchitecture.  They also
;; describe the following rules mentioned in Itanium
;; microarchitecture: rules mentioned in Itanium microarchitecture:
;; o "MMF: Always splits issue before the first M and after F regardless
;;   of surrounding bundles and stops".
;; o "BBB/MBB: Always splits issue after either of these bundles".
;; o "MIB BBB: Split issue after the first bundle in this pair".

(exclusion_set "1_0m.mf,1_0mm.f,1_0mmf."
   "1_1m.ii,1_1m.mi,1_1m.fi,1_1b.bb,1_1m.bb,1_1m.ib,1_1m.mb,1_1m.fb,1_1m.lx")
(exclusion_set "1_0b.bb,1_0bb.b,1_0bbb.,1_0m.bb,1_0mb.b,1_0mbb."
   "1_1m.ii,1_1m.mi,1_1m.fi,1_1b.bb,1_1m.bb,1_1m.ib,1_1m.mb,1_1m.fb,1_1m.lx")
(exclusion_set "1_0m.ib,1_0mi.b,1_0mib." "1_1b.bb")

;;  For exceptions of M, I, B, F insns:
(define_cpu_unit "1_not_um1, 1_not_ui1, 1_not_uf1" "one")

(final_absence_set "1_not_um1"  "1_um1")
(final_absence_set "1_not_ui1"  "1_ui1")
(final_absence_set "1_not_uf1"  "1_uf1")

;;; "MIB/MFB/MMB: Splits issue after any of these bundles unless the
;;; B-slot contains a nop.b or a brp instruction".
;;;   "The B in an MIB/MFB/MMB bundle disperses to B0 if it is a brp or
;;; nop.b, otherwise it disperses to B2".
(final_absence_set
   "1_1m.ii, 1_1m.mi, 1_1m.fi, 1_1b.bb, 1_1m.bb, 1_1m.ib, 1_1m.mb, 1_1m.fb,\
    1_1m.lx"
   "1_0mib. 1_ub2, 1_0mfb. 1_ub2, 1_0mmb. 1_ub2")

;; This is necessary to start new processor cycle when we meet stop bit.
(define_cpu_unit "1_stop" "one")
(final_absence_set
   "1_0m.ii,1_0mi.i,1_0mii.,1_0m.mi,1_0mm.i,1_0mmi.,1_0m.fi,1_0mf.i,1_0mfi.,\
    1_0m.mf,1_0mm.f,1_0mmf.,1_0b.bb,1_0bb.b,1_0bbb.,1_0m.bb,1_0mb.b,1_0mbb.,\
    1_0m.ib,1_0mi.b,1_0mib.,1_0m.mb,1_0mm.b,1_0mmb.,1_0m.fb,1_0mf.b,1_0mfb.,\
    1_0m.lx,1_0mlx., \
    1_1m.ii,1_1mi.i,1_1mii.,1_1m.mi,1_1mm.i,1_1mmi.,1_1m.fi,1_1mf.i,1_1mfi.,\
    1_1b.bb,1_1bb.b,1_1bbb.,1_1m.bb,1_1mb.b,1_1mbb.,1_1m.ib,1_1mi.b,1_1mib.,\
    1_1m.mb,1_1mm.b,1_1mmb.,1_1m.fb,1_1mf.b,1_1mfb.,1_1m.lx,1_1mlx."
   "1_stop")

;; M and I instruction is dispersed to the lowest numbered M or I unit
;; not already in use.  An I slot in the 3rd position of 2nd bundle is
;; always dispersed to I1
(final_presence_set "1_um1" "1_um0")
(final_presence_set "1_ui1" "1_ui0, 1_1mii., 1_1mmi., 1_1mfi.")

;; Insns

;; M and I instruction is dispersed to the lowest numbered M or I unit
;; not already in use.  An I slot in the 3rd position of 2nd bundle is
;; always dispersed to I1
(define_reservation "1_M0"
  "1_0m.ii+1_um0|1_0m.mi+1_um0|1_0mm.i+(1_um0|1_um1)\
   |1_0m.fi+1_um0|1_0m.mf+1_um0|1_0mm.f+1_um1\
   |1_0m.bb+1_um0|1_0m.ib+1_um0|1_0m.mb+1_um0\
   |1_0mm.b+1_um1|1_0m.fb+1_um0|1_0m.lx+1_um0\
   |1_1mm.i+1_um1|1_1mm.b+1_um1\
   |(1_1m.ii|1_1m.mi|1_1m.fi|1_1m.bb|1_1m.ib|1_1m.mb|1_1m.fb|1_1m.lx)\
    +(1_um0|1_um1)")

(define_reservation "1_M1"
  "(1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0\
    |1_0mib.+1_unb0|1_0mfb.+1_unb0|1_0mmb.+1_unb0)\
     +(1_1m.ii|1_1m.mi|1_1m.fi|1_1m.bb|1_1m.ib|1_1m.mb|1_1m.fb|1_1m.lx)\
     +(1_um0|1_um1)")

(define_reservation "1_M" "1_M0|1_M1")

;;  Exceptions for dispersal rules.
;; "An I slot in the 3rd position of 2nd bundle is always dispersed to I1".
(define_reservation "1_I0"
  "1_0mi.i+1_ui0|1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0\
   |1_0mi.b+1_ui0|(1_1mi.i|1_1mi.b)+(1_ui0|1_ui1)\
   |1_1mii.+1_ui1|1_1mmi.+1_ui1|1_1mfi.+1_ui1")

(define_reservation "1_I1"
  "1_0m.ii+1_um0+1_0mi.i+1_ui0|1_0mm.i+(1_um0|1_um1)+1_0mmi.+1_ui0\
   |1_0mf.i+1_uf0+1_0mfi.+1_ui0|1_0m.ib+1_um0+1_0mi.b+1_ui0\
   |(1_1m.ii+(1_um0|1_um1)+1_1mi.i\
   |1_1m.ib+(1_um0|1_um1)+1_1mi.b)+(1_ui0|1_ui1)\
   |1_1mm.i+1_um1+1_1mmi.+1_ui1|1_1mf.i+1_uf1+1_1mfi.+1_ui1")

(define_reservation "1_I" "1_I0|1_I1")

;; "An F slot in the 1st bundle disperses to F0".
;; "An F slot in the 2st bundle disperses to F1".
(define_reservation "1_F0"
   "1_0mf.i+1_uf0|1_0mmf.+1_uf0|1_0mf.b+1_uf0|1_1mf.i+1_uf1|1_1mf.b+1_uf1")

(define_reservation "1_F1"
   "1_0m.fi+1_um0+1_0mf.i+1_uf0|1_0mm.f+(1_um0|1_um1)+1_0mmf.+1_uf0\
    |1_0m.fb+1_um0+1_0mf.b+1_uf0|1_1m.fi+(1_um0|1_um1)+1_1mf.i+1_uf1\
    |1_1m.fb+(1_um0|1_um1)+1_1mf.b+1_uf1")

(define_reservation "1_F2"
   "1_0m.mf+1_um0+1_0mm.f+1_um1+1_0mmf.+1_uf0\
    |(1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0\
      |1_0mib.+1_unb0|1_0mmb.+1_unb0|1_0mfb.+1_unb0)\
     +(1_1m.fi+(1_um0|1_um1)+1_1mf.i+1_uf1\
       |1_1m.fb+(1_um0|1_um1)+1_1mf.b+1_uf1)")

(define_reservation "1_F" "1_F0|1_F1|1_F2")

;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B
;;; unit. That is, a B slot in 1st position is dispersed to B0.  In the
;;; 2nd position it is dispersed to B2".
(define_reservation "1_NB"
    "1_0b.bb+1_unb0|1_0bb.b+1_unb1|1_0bbb.+1_unb2\
     |1_0mb.b+1_unb1|1_0mbb.+1_unb2\
     |1_0mib.+1_unb0|1_0mmb.+1_unb0|1_0mfb.+1_unb0\
     |1_1b.bb+1_unb0|1_1bb.b+1_unb1\
     |1_1bbb.+1_unb2|1_1mb.b+1_unb1|1_1mbb.+1_unb2|1_1mib.+1_unb0\
     |1_1mmb.+1_unb0|1_1mfb.+1_unb0")

(define_reservation "1_B0"
   "1_0b.bb+1_ub0|1_0bb.b+1_ub1|1_0bbb.+1_ub2\
    |1_0mb.b+1_ub1|1_0mbb.+1_ub2|1_0mib.+1_ub2\
    |1_0mfb.+1_ub2|1_1b.bb+1_ub0|1_1bb.b+1_ub1\
    |1_1bbb.+1_ub2|1_1mb.b+1_ub1\
    |1_1mib.+1_ub2|1_1mmb.+1_ub2|1_1mfb.+1_ub2")

(define_reservation "1_B1"
   "1_0m.bb+1_um0+1_0mb.b+1_ub1|1_0mi.b+1_ui0+1_0mib.+1_ub2\
    |1_0mf.b+1_uf0+1_0mfb.+1_ub2\
    |(1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0)+1_1b.bb+1_ub0\
    |1_1m.bb+(1_um0|1_um1)+1_1mb.b+1_ub1\
    |1_1mi.b+(1_ui0|1_ui1)+1_1mib.+1_ub2\
    |1_1mm.b+1_um1+1_1mmb.+1_ub2\
    |1_1mf.b+1_uf1+1_1mfb.+1_ub2")

(define_reservation "1_B" "1_B0|1_B1")

;; MLX bunlde uses ports equivalent to MFI bundles.
(define_reservation "1_L0" "1_0mlx.+1_ui0+1_uf0|1_1mlx.+(1_ui0|1_ui1)+1_uf1")
(define_reservation "1_L1"
   "1_0m.lx+1_um0+1_0mlx.+1_ui0+1_uf0\
   |1_1m.lx+(1_um0|1_um1)+1_1mlx.+(1_ui0|1_ui1)+1_uf1")
(define_reservation "1_L2"
   "(1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0\
     |1_0mib.+1_unb0|1_0mmb.+1_unb0|1_0mfb.+1_unb0)
    +1_1m.lx+(1_um0|1_um1)+1_1mlx.+1_ui1+1_uf1")
(define_reservation "1_L" "1_L0|1_L1|1_L2")

(define_reservation "1_A" "1_M|1_I")

(define_insn_reservation "1_stop_bit" 0
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "stop_bit"))
       (eq (symbol_ref "bundling_p") (const_int 0)))
  "1_stop|1_m0_stop|1_m1_stop|1_mi0_stop|1_mi1_stop")

(define_insn_reservation "1_br"      0
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "br"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_B")
(define_insn_reservation "1_scall"   0
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "scall"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_B")
(define_insn_reservation "1_fcmp"    2
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "fcmp"))
       (eq (symbol_ref "bundling_p") (const_int 0)))
  "1_F+1_not_uf1")
(define_insn_reservation "1_fcvtfx"  7
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "fcvtfx"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_F")
(define_insn_reservation "1_fld"     9
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "fld"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_fldp"    9
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "fldp"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_fmac"    5
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "fmac"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_F")
(define_insn_reservation "1_fmisc"   5
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "fmisc"))
       (eq (symbol_ref "bundling_p") (const_int 0)))
  "1_F+1_not_uf1")

;; There is only one insn `mov = ar.bsp' for frar_i:
(define_insn_reservation "1_frar_i" 13
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "frar_i"))
       (eq (symbol_ref "bundling_p") (const_int 0)))
  "1_I+1_not_ui1")
;; There is only two insns `mov = ar.unat' or `mov = ar.ccv' for frar_m:
(define_insn_reservation "1_frar_m"  6
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "frar_m"))
       (eq (symbol_ref "bundling_p") (const_int 0)))
  "1_M+1_not_um1")
(define_insn_reservation "1_frbr"    2
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "frbr"))
       (eq (symbol_ref "bundling_p") (const_int 0)))
  "1_I+1_not_ui1")
(define_insn_reservation "1_frfr"    2
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "frfr"))
       (eq (symbol_ref "bundling_p") (const_int 0)))
  "1_M+1_not_um1")
(define_insn_reservation "1_frpr"    2
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "frpr"))
       (eq (symbol_ref "bundling_p") (const_int 0)))
  "1_I+1_not_ui1")

(define_insn_reservation "1_ialu"      1
    (and (and (eq_attr "cpu" "itanium")
              (eq_attr "itanium_class" "ialu"))
         (eq (symbol_ref
              "bundling_p || ia64_produce_address_p (insn)")
              (const_int 0)))
    "1_A")
(define_insn_reservation "1_ialu_addr" 1
    (and (and (eq_attr "cpu" "itanium")
              (eq_attr "itanium_class" "ialu"))
         (eq (symbol_ref
              "!bundling_p && ia64_produce_address_p (insn)")
             (const_int 1)))
    "1_M")
(define_insn_reservation "1_icmp"    1
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "icmp"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_A")
(define_insn_reservation "1_ilog"    1
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "ilog"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_A")
(define_insn_reservation "1_mmalua" 2
    (and (and (eq_attr "cpu" "itanium")
              (eq_attr "itanium_class" "mmalua"))
         (eq (symbol_ref "bundling_p") (const_int 0)))
    "1_A")
(define_insn_reservation "1_ishf"    1
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "ishf"))
       (eq (symbol_ref "bundling_p") (const_int 0)))
    "1_I+1_not_ui1")
(define_insn_reservation "1_ld"      2
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "ld"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_long_i"  1
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "long_i"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_L")
(define_insn_reservation "1_mmmul"   2
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "mmmul"))
       (eq (symbol_ref "bundling_p") (const_int 0)))
  "1_I+1_not_ui1")
(define_insn_reservation "1_mmshf"   2
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "mmshf"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_I")
(define_insn_reservation "1_mmshfi"  1
  (and (and (eq_attr "cpu" "itanium")
            (eq_attr "itanium_class" "mmshfi"))
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_I")

;; Now we have only one insn (flushrs) of such class.  We assume that flushrs
;; is the 1st syllable of the bundle after stop bit.
(define_insn_reservation "1_rse_m"   0