predicates.md

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;; Predicate definitions for Frv.
;; Copyright (C) 2005 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING.  If not, write to
;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
;; Boston, MA 02110-1301, USA.

;; Return true if operand is a GPR register.

(define_predicate "integer_register_operand"
  (match_code "reg,subreg")
{
  if (GET_MODE (op) != mode && mode != VOIDmode)
    return FALSE;

  if (GET_CODE (op) == SUBREG)
    {
      if (GET_CODE (SUBREG_REG (op)) != REG)
	return register_operand (op, mode);

      op = SUBREG_REG (op);
    }

  if (GET_CODE (op) != REG)
    return FALSE;

  return GPR_AP_OR_PSEUDO_P (REGNO (op));
})

;; Return 1 is OP is a memory operand, or will be turned into one by
;; reload.

(define_predicate "frv_load_operand"
  (match_code "reg,subreg,mem")
{
  if (GET_MODE (op) != mode && mode != VOIDmode)
    return FALSE;

  if (reload_in_progress)
    {
      rtx tmp = op;
      if (GET_CODE (tmp) == SUBREG)
	tmp = SUBREG_REG (tmp);
      if (GET_CODE (tmp) == REG
	  && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
	op = reg_equiv_memory_loc[REGNO (tmp)];
    }

  return op && memory_operand (op, mode);
})

;; Return true if operand is a GPR register.  Do not allow SUBREG's
;; here, in order to prevent a combine bug.

(define_predicate "gpr_no_subreg_operand"
  (match_code "reg")
{
  if (GET_MODE (op) != mode && mode != VOIDmode)
    return FALSE;

  if (GET_CODE (op) != REG)
    return FALSE;

  return GPR_OR_PSEUDO_P (REGNO (op));
})

;; Return 1 if operand is a GPR register or a FPR register.

(define_predicate "gpr_or_fpr_operand"
  (match_code "reg,subreg")
{
  int regno;

  if (GET_MODE (op) != mode && mode != VOIDmode)
    return FALSE;

  if (GET_CODE (op) == SUBREG)
    {
      if (GET_CODE (SUBREG_REG (op)) != REG)
	return register_operand (op, mode);

      op = SUBREG_REG (op);
    }

  if (GET_CODE (op) != REG)
    return FALSE;

  regno = REGNO (op);
  if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
    return TRUE;

  return FALSE;
})

;; Return 1 if operand is a GPR register or 12 bit signed immediate.

(define_predicate "gpr_or_int12_operand"
  (match_code "reg,subreg,const_int,const")
{
  if (GET_CODE (op) == CONST_INT)
    return IN_RANGE_P (INTVAL (op), -2048, 2047);

  if (got12_operand (op, mode))
    return true;

  if (GET_MODE (op) != mode && mode != VOIDmode)
    return FALSE;

  if (GET_CODE (op) == SUBREG)
    {
      if (GET_CODE (SUBREG_REG (op)) != REG)
	return register_operand (op, mode);

      op = SUBREG_REG (op);
    }

  if (GET_CODE (op) != REG)
    return FALSE;

  return GPR_OR_PSEUDO_P (REGNO (op));
})

;; Return 1 if operand is a GPR register, or a FPR register, or a 12
;; bit signed immediate.

(define_predicate "gpr_fpr_or_int12_operand"
  (match_code "reg,subreg,const_int")
{
  int regno;

  if (GET_CODE (op) == CONST_INT)
    return IN_RANGE_P (INTVAL (op), -2048, 2047);

  if (GET_MODE (op) != mode && mode != VOIDmode)
    return FALSE;

  if (GET_CODE (op) == SUBREG)
    {
      if (GET_CODE (SUBREG_REG (op)) != REG)
	return register_operand (op, mode);

      op = SUBREG_REG (op);
    }

  if (GET_CODE (op) != REG)
    return FALSE;

  regno = REGNO (op);
  if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
    return TRUE;

  return FALSE;
})

;; Return 1 if operand is a register or 10 bit signed immediate.

(define_predicate "gpr_or_int10_operand"
  (match_code "reg,subreg,const_int")
{
  if (GET_CODE (op) == CONST_INT)
    return IN_RANGE_P (INTVAL (op), -512, 511);

  if (GET_MODE (op) != mode && mode != VOIDmode)
    return FALSE;

  if (GET_CODE (op) == SUBREG)
    {
      if (GET_CODE (SUBREG_REG (op)) != REG)
	return register_operand (op, mode);

      op = SUBREG_REG (op);
    }

  if (GET_CODE (op) != REG)
    return FALSE;

  return GPR_OR_PSEUDO_P (REGNO (op));
})

;; Return 1 if operand is a register or an integer immediate.

(define_predicate "gpr_or_int_operand"
  (match_code "reg,subreg,const_int")
{
  if (GET_CODE (op) == CONST_INT)
    return TRUE;

  if (GET_MODE (op) != mode && mode != VOIDmode)
    return FALSE;

  if (GET_CODE (op) == SUBREG)
    {
      if (GET_CODE (SUBREG_REG (op)) != REG)
	return register_operand (op, mode);

      op = SUBREG_REG (op);
    }

  if (GET_CODE (op) != REG)
    return FALSE;

  return GPR_OR_PSEUDO_P (REGNO (op));
})

;; Return true if operand is something that can be an input for a move
;; operation.

(define_predicate "move_source_operand"
  (match_code "reg,subreg,const_int,mem,const_double,const,symbol_ref,label_ref")
{
  rtx subreg;
  enum rtx_code code;

  switch (GET_CODE (op))
    {
    default:
      break;

    case CONST_INT:
    case CONST_DOUBLE:
      return immediate_operand (op, mode);

    case SUBREG:
      if (GET_MODE (op) != mode && mode != VOIDmode)
        return FALSE;

      subreg = SUBREG_REG (op);
      code = GET_CODE (subreg);
      if (code == MEM)
	return frv_legitimate_address_p (mode, XEXP (subreg, 0),
					 reload_completed, FALSE, FALSE);

      return (code == REG);

    case REG:
      if (GET_MODE (op) != mode && mode != VOIDmode)
        return FALSE;

      return TRUE;

    case MEM:
      return frv_legitimate_memory_operand (op, mode, FALSE);
    }

  return FALSE;
})

;; Return true if operand is something that can be an output for a
;; move operation.

(define_predicate "move_destination_operand"
  (match_code "reg,subreg,mem")
{
  rtx subreg;
  enum rtx_code code;

  switch (GET_CODE (op))
    {
    default:
      break;

    case SUBREG:
      if (GET_MODE (op) != mode && mode != VOIDmode)
        return FALSE;

      subreg = SUBREG_REG (op);
      code = GET_CODE (subreg);
      if (code == MEM)
	return frv_legitimate_address_p (mode, XEXP (subreg, 0),
					 reload_completed, FALSE, FALSE);

      return (code == REG);

    case REG:
      if (GET_MODE (op) != mode && mode != VOIDmode)
        return FALSE;

      return TRUE;

    case MEM:
      return frv_legitimate_memory_operand (op, mode, FALSE);
    }

  return FALSE;
})

;; Return true if we the operand is a valid destination for a movcc_fp
;; instruction.  This means rejecting fcc_operands, since we need
;; scratch registers to write to them.

(define_predicate "movcc_fp_destination_operand"
  (match_code "reg,subreg,mem")
{
  if (fcc_operand (op, mode))
    return FALSE;

  return move_destination_operand (op, mode);
})

;; Return true if operand is something that can be an input for a
;; conditional move operation.

(define_predicate "condexec_source_operand"
  (match_code "reg,subreg,const_int,mem,const_double")
{
  rtx subreg;
  enum rtx_code code;

  switch (GET_CODE (op))
    {
    default:
      break;

    case CONST_INT:
    case CONST_DOUBLE:
      return ZERO_P (op);

    case SUBREG:
      if (GET_MODE (op) != mode && mode != VOIDmode)
        return FALSE;

      subreg = SUBREG_REG (op);
      code = GET_CODE (subreg);
      if (code == MEM)
	return frv_legitimate_address_p (mode, XEXP (subreg, 0),
					 reload_completed, TRUE, FALSE);

      return (code == REG);

    case REG:
      if (GET_MODE (op) != mode && mode != VOIDmode)
        return FALSE;

      return TRUE;

    case MEM:
      return frv_legitimate_memory_operand (op, mode, TRUE);
    }

  return FALSE;
})

;; Return true if operand is something that can be an output for a
;; conditional move operation.

(define_predicate "condexec_dest_operand"
  (match_code "reg,subreg,mem")
{
  rtx subreg;
  enum rtx_code code;

  switch (GET_CODE (op))
    {
    default:
      break;

    case SUBREG:
      if (GET_MODE (op) != mode && mode != VOIDmode)
        return FALSE;

      subreg = SUBREG_REG (op);
      code = GET_CODE (subreg);
      if (code == MEM)
	return frv_legitimate_address_p (mode, XEXP (subreg, 0),
					 reload_completed, TRUE, FALSE);

      return (code == REG);

    case REG:
      if (GET_MODE (op) != mode && mode != VOIDmode)
        return FALSE;

      return TRUE;

    case MEM:
      return frv_legitimate_memory_operand (op, mode, TRUE);
    }

  return FALSE;
})

;; Return true if operand is a register of any flavor or a 0 of the
;; appropriate type.

(define_predicate "reg_or_0_operand"
  (match_code "reg,subreg,const_int")
{
  switch (GET_CODE (op))
    {
    default:
      break;

    case REG:
    case SUBREG:
      if (GET_MODE (op) != mode && mode != VOIDmode)
	return FALSE;

      return register_operand (op, mode);

    case CONST_INT:
    case CONST_DOUBLE:
      return ZERO_P (op);
    }

  return FALSE;
})

;; Return true if operand is the link register.

(define_predicate "lr_operand"
  (match_code "reg")
{
  if (GET_CODE (op) != REG)
    return FALSE;

  if (GET_MODE (op) != mode && mode != VOIDmode)
    return FALSE;

  if (REGNO (op) != LR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
    return FALSE;

  return TRUE;
})

;; Return true if operand is a gpr register or a valid memory operand.

(define_predicate "gpr_or_memory_operand"
  (match_code "reg,subreg,mem")
{
  return (integer_register_operand (op, mode)
	  || frv_legitimate_memory_operand (op, mode, FALSE));
})

;; Return true if operand is a gpr register, a valid memory operand,
;; or a memory operand that can be made valid using an additional gpr
;; register.

(define_predicate "gpr_or_memory_operand_with_scratch"
  (match_code "reg,subreg,mem")
{
  rtx addr;

  if (gpr_or_memory_operand (op, mode))
    return TRUE;

  if (GET_CODE (op) != MEM)
    return FALSE;

  if (GET_MODE (op) != mode)
    return FALSE;

  addr = XEXP (op, 0);

  if (GET_CODE (addr) != PLUS)
    return FALSE;
      
  if (!integer_register_operand (XEXP (addr, 0), Pmode))
    return FALSE;

  if (GET_CODE (XEXP (addr, 1)) != CONST_INT)
    return FALSE;

  return TRUE;
})

;; Return true if operand is a fpr register or a valid memory
;; operation.

(define_predicate "fpr_or_memory_operand"
  (match_code "reg,subreg,mem")
{
  return (fpr_operand (op, mode)
	  || frv_legitimate_memory_operand (op, mode, FALSE));
})

;; Return 1 if operand is a 12 bit signed immediate.

(define_predicate "int12_operand"
  (match_code "const_int")
{
  if (GET_CODE (op) != CONST_INT)
    return FALSE;

  return IN_RANGE_P (INTVAL (op), -2048, 2047);
})

;; Return 1 if operand is an integer constant that takes 2
;; instructions to load up and can be split into sethi/setlo
;; instructions..

(define_predicate "int_2word_operand"
  (match_code "const_int,const_double,symbol_ref,label_ref,const")
{
  HOST_WIDE_INT value;
  REAL_VALUE_TYPE rv;
  long l;

  switch (GET_CODE (op))
    {
    default:
      break;

    case LABEL_REF:
      if (TARGET_FDPIC)