mips-dsp.md

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  "@
   repl.ph\t%0,%1
   replv.ph\t%0,%1"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

;; Table 2-5. MIPS DSP ASE Instructions: Compare-Pick
;; CMPU.* CMP.*
(define_insn "mips_cmp<DSPV:dspfmt1_1>_eq_<DSPV:dspfmt2>"
  [(set (reg:CCDSP CCDSP_CC_REGNUM)
	(unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d")
		       (match_operand:DSPV 1 "register_operand" "d")
		       (reg:CCDSP CCDSP_CC_REGNUM)]
		      UNSPEC_CMP_EQ))]
  "TARGET_DSP"
  "cmp<DSPV:dspfmt1_1>.eq.<DSPV:dspfmt2>\t%0,%1"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

(define_insn "mips_cmp<DSPV:dspfmt1_1>_lt_<DSPV:dspfmt2>"
  [(set (reg:CCDSP CCDSP_CC_REGNUM)
	(unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d")
		       (match_operand:DSPV 1 "register_operand" "d")
		       (reg:CCDSP CCDSP_CC_REGNUM)]
		      UNSPEC_CMP_LT))]
  "TARGET_DSP"
  "cmp<DSPV:dspfmt1_1>.lt.<DSPV:dspfmt2>\t%0,%1"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

(define_insn "mips_cmp<DSPV:dspfmt1_1>_le_<DSPV:dspfmt2>"
  [(set (reg:CCDSP CCDSP_CC_REGNUM)
	(unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d")
		       (match_operand:DSPV 1 "register_operand" "d")
		       (reg:CCDSP CCDSP_CC_REGNUM)]
		      UNSPEC_CMP_LE))]
  "TARGET_DSP"
  "cmp<DSPV:dspfmt1_1>.le.<DSPV:dspfmt2>\t%0,%1"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

(define_insn "mips_cmpgu_eq_qb"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
		    (match_operand:V4QI 2 "register_operand" "d")]
		   UNSPEC_CMPGU_EQ_QB))]
  "TARGET_DSP"
  "cmpgu.eq.qb\t%0,%1,%2"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

(define_insn "mips_cmpgu_lt_qb"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
		    (match_operand:V4QI 2 "register_operand" "d")]
		   UNSPEC_CMPGU_LT_QB))]
  "TARGET_DSP"
  "cmpgu.lt.qb\t%0,%1,%2"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

(define_insn "mips_cmpgu_le_qb"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
		    (match_operand:V4QI 2 "register_operand" "d")]
		   UNSPEC_CMPGU_LE_QB))]
  "TARGET_DSP"
  "cmpgu.le.qb\t%0,%1,%2"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

;; PICK*
(define_insn "mips_pick_<DSPV:dspfmt2>"
  [(set (match_operand:DSPV 0 "register_operand" "=d")
	(unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d")
		      (match_operand:DSPV 2 "register_operand" "d")
		      (reg:CCDSP CCDSP_CC_REGNUM)]
		     UNSPEC_PICK))]
  "TARGET_DSP"
  "pick.<DSPV:dspfmt2>\t%0,%1,%2"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

;; PACKRL*
(define_insn "mips_packrl_ph"
  [(set (match_operand:V2HI 0 "register_operand" "=d")
	(unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d")
		      (match_operand:V2HI 2 "register_operand" "d")]
		     UNSPEC_PACKRL_PH))]
  "TARGET_DSP"
  "packrl.ph\t%0,%1,%2"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

;; Table 2-6. MIPS DSP ASE Instructions: Accumulator and DSPControl Access
;; EXTR*
(define_insn "mips_extr_w"
  [(parallel
    [(set (match_operand:SI 0 "register_operand" "=d,d")
	  (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
		      (match_operand:SI 2 "arith_operand" "I,d")]
		     UNSPEC_EXTR_W))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_W))])]
  "TARGET_DSP && !TARGET_64BIT"
{
  if (which_alternative == 0)
    {
      if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
	operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
      return "extr.w\t%0,%q1,%2";
    }
  return "extrv.w\t%0,%q1,%2";
}
  [(set_attr "type"	"mfhilo")
   (set_attr "mode"	"SI")])

(define_insn "mips_extr_r_w"
  [(parallel
    [(set (match_operand:SI 0 "register_operand" "=d,d")
	  (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
		      (match_operand:SI 2 "arith_operand" "I,d")]
		     UNSPEC_EXTR_R_W))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_R_W))])]
  "TARGET_DSP && !TARGET_64BIT"
{
  if (which_alternative == 0)
    {
      if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
	operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
      return "extr_r.w\t%0,%q1,%2";
    }
  return "extrv_r.w\t%0,%q1,%2";
}
  [(set_attr "type"	"mfhilo")
   (set_attr "mode"	"SI")])

(define_insn "mips_extr_rs_w"
  [(parallel
    [(set (match_operand:SI 0 "register_operand" "=d,d")
	  (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
		      (match_operand:SI 2 "arith_operand" "I,d")]
		     UNSPEC_EXTR_RS_W))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_RS_W))])]
  "TARGET_DSP && !TARGET_64BIT"
{
  if (which_alternative == 0)
    {
      if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
	operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
      return "extr_rs.w\t%0,%q1,%2";
    }
  return "extrv_rs.w\t%0,%q1,%2";
}
  [(set_attr "type"	"mfhilo")
   (set_attr "mode"	"SI")])

;; EXTR*_S.H
(define_insn "mips_extr_s_h"
  [(parallel
    [(set (match_operand:SI 0 "register_operand" "=d,d")
	  (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
		      (match_operand:SI 2 "arith_operand" "I,d")]
		     UNSPEC_EXTR_S_H))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_S_H))])]
  "TARGET_DSP && !TARGET_64BIT"
{
  if (which_alternative == 0)
    {
      if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
	operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
      return "extr_s.h\t%0,%q1,%2";
    }
  return "extrv_s.h\t%0,%q1,%2";
}
  [(set_attr "type"	"mfhilo")
   (set_attr "mode"	"SI")])

;; EXTP*
(define_insn "mips_extp"
  [(parallel
    [(set (match_operand:SI 0 "register_operand" "=d,d")
	  (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
		      (match_operand:SI 2 "arith_operand" "I,d")
		      (reg:CCDSP CCDSP_PO_REGNUM)]
		     UNSPEC_EXTP))
     (set (reg:CCDSP CCDSP_EF_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTP))])]
  "TARGET_DSP && !TARGET_64BIT"
{
  if (which_alternative == 0)
    {
      if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
	operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
      return "extp\t%0,%q1,%2";
    }
  return "extpv\t%0,%q1,%2";
}
  [(set_attr "type"	"mfhilo")
   (set_attr "mode"	"SI")])

(define_insn "mips_extpdp"
  [(parallel
    [(set (match_operand:SI 0 "register_operand" "=d,d")
	  (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
		      (match_operand:SI 2 "arith_operand" "I,d")
		      (reg:CCDSP CCDSP_PO_REGNUM)]
		     UNSPEC_EXTPDP))
     (set (reg:CCDSP CCDSP_PO_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)
			 (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_EXTPDP))
     (set (reg:CCDSP CCDSP_EF_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTPDP))])]
  "TARGET_DSP && !TARGET_64BIT"
{
  if (which_alternative == 0)
    {
      if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
	operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
      return "extpdp\t%0,%q1,%2";
    }
  return "extpdpv\t%0,%q1,%2";
}
  [(set_attr "type"	"mfhilo")
   (set_attr "mode"	"SI")])

;; SHILO*
(define_insn "mips_shilo"
  [(set (match_operand:DI 0 "register_operand" "=a,a")
	(unspec:DI [(match_operand:DI 1 "register_operand" "0,0")
		    (match_operand:SI 2 "arith_operand" "I,d")]
		   UNSPEC_SHILO))]
  "TARGET_DSP && !TARGET_64BIT"
{
  if (which_alternative == 0)
    {
      if (INTVAL (operands[2]) < -32 || INTVAL (operands[2]) > 31)
	operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
      return "shilo\t%q0,%2";
    }
  return "shilov\t%q0,%2";
}
  [(set_attr "type"	"mfhilo")
   (set_attr "mode"	"SI")])

;; MTHLIP*
(define_insn "mips_mthlip"
  [(parallel
    [(set (match_operand:DI 0 "register_operand" "=a")
	  (unspec:DI [(match_operand:DI 1 "register_operand" "0")
		      (match_operand:SI 2 "register_operand" "d")
		      (reg:CCDSP CCDSP_PO_REGNUM)]
		     UNSPEC_MTHLIP))
     (set (reg:CCDSP CCDSP_PO_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)
			 (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_MTHLIP))])]
  "TARGET_DSP && !TARGET_64BIT"
  "mthlip\t%2,%q0"
  [(set_attr "type"	"mfhilo")
   (set_attr "mode"	"SI")])

;; WRDSP
(define_insn "mips_wrdsp"
  [(parallel
    [(set (reg:CCDSP CCDSP_PO_REGNUM)
	  (unspec:CCDSP [(match_operand:SI 0 "register_operand" "d")
			 (match_operand:SI 1 "const_uimm6_operand" "YA")]
			 UNSPEC_WRDSP))
     (set (reg:CCDSP CCDSP_SC_REGNUM)
	  (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
     (set (reg:CCDSP CCDSP_CA_REGNUM)
	  (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
     (set (reg:CCDSP CCDSP_CC_REGNUM)
	  (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
     (set (reg:CCDSP CCDSP_EF_REGNUM)
	  (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))])]
  "TARGET_DSP"
  "wrdsp\t%0,%1"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

;; RDDSP
(define_insn "mips_rddsp"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(unspec:SI [(match_operand:SI 1 "const_uimm6_operand" "YA")
		    (reg:CCDSP CCDSP_PO_REGNUM)
		    (reg:CCDSP CCDSP_SC_REGNUM)
		    (reg:CCDSP CCDSP_CA_REGNUM)
		    (reg:CCDSP CCDSP_OU_REGNUM)
		    (reg:CCDSP CCDSP_CC_REGNUM)
		    (reg:CCDSP CCDSP_EF_REGNUM)]
		   UNSPEC_RDDSP))]
  "TARGET_DSP"
  "rddsp\t%0,%1"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

;; Table 2-7. MIPS DSP ASE Instructions: Indexed-Load
;; L*X
(define_insn "mips_lbux"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(zero_extend:SI (mem:QI (plus:SI (match_operand:SI 1
					  "register_operand" "d")
					 (match_operand:SI 2
					  "register_operand" "d")))))]
  "TARGET_DSP"
  "lbux\t%0,%2(%1)"
  [(set_attr "type"	"load")
   (set_attr "mode"	"SI")
   (set_attr "length"	"4")])

(define_insn "mips_lhx"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(sign_extend:SI (mem:HI (plus:SI (match_operand:SI 1
					  "register_operand" "d")
					 (match_operand:SI 2
					  "register_operand" "d")))))]
  "TARGET_DSP"
  "lhx\t%0,%2(%1)"
  [(set_attr "type"	"load")
   (set_attr "mode"	"SI")
   (set_attr "length"	"4")])

(define_insn "mips_lwx"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "d")
			 (match_operand:SI 2 "register_operand" "d"))))]
  "TARGET_DSP"
  "lwx\t%0,%2(%1)"
  [(set_attr "type"	"load")
   (set_attr "mode"	"SI")
   (set_attr "length"	"4")])

;; Table 2-8. MIPS DSP ASE Instructions: Branch
;; BPOSGE32
(define_insn "mips_bposge"
  [(set (pc)
	(if_then_else
	   (ge:CCDSP (reg:CCDSP CCDSP_PO_REGNUM)
		     (match_operand:SI 0 "immediate_operand" "I"))
	   (label_ref (match_operand 1 "" ""))
	   (pc)))]
  "TARGET_DSP"
  "%*bposge%0\t%1%/"
  [(set_attr "type"	"branch")
   (set_attr "mode"	"none")])