mips-dsp.md

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    }
  return "shrlv.qb\t%0,%1,%2";
}
  [(set_attr "type"	"shift")
   (set_attr "mode"	"SI")])

;; SHRA*
(define_insn "mips_shra_ph"
  [(set (match_operand:V2HI 0 "register_operand" "=d,d")
	(unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d,d")
		      (match_operand:SI 2 "arith_operand" "I,d")]
		     UNSPEC_SHRA_PH))]
  "TARGET_DSP"
{
  if (which_alternative == 0)
    {
      if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0xf)
	operands[2] = GEN_INT (INTVAL (operands[2]) & 0xf);
      return "shra.ph\t%0,%1,%2";
    }
  return "shrav.ph\t%0,%1,%2";
}
  [(set_attr "type"	"shift")
   (set_attr "mode"	"SI")])

(define_insn "mips_shra_r_<DSPQ:dspfmt2>"
  [(set (match_operand:DSPQ 0 "register_operand" "=d,d")
	(unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d")
		      (match_operand:SI 2 "arith_operand" "I,d")]
		     UNSPEC_SHRA_R))]
  "TARGET_DSP"
{
  if (which_alternative == 0)
    {
      if (INTVAL (operands[2])
	  & ~(unsigned HOST_WIDE_INT) <DSPQ:dspshift_mask>)
	operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPQ:dspshift_mask>);
      return "shra_r.<DSPQ:dspfmt2>\t%0,%1,%2";
    }
  return "shrav_r.<DSPQ:dspfmt2>\t%0,%1,%2";
}
  [(set_attr "type"	"shift")
   (set_attr "mode"	"SI")])

;; Table 2-3. MIPS DSP ASE Instructions: Multiply
;; MULEU*
(define_insn "mips_muleu_s_ph_qbl"
  [(parallel
    [(set (match_operand:V2HI 0 "register_operand" "=d")
	  (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")
			(match_operand:V2HI 2 "register_operand" "d")]
		       UNSPEC_MULEU_S_PH_QBL))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBL))
     (clobber (match_scratch:DI 3 "=x"))])]
  "TARGET_DSP"
  "muleu_s.ph.qbl\t%0,%1,%2"
  [(set_attr "type"	"imul3")
   (set_attr "mode"	"SI")])

(define_insn "mips_muleu_s_ph_qbr"
  [(parallel
    [(set (match_operand:V2HI 0 "register_operand" "=d")
	  (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")
			(match_operand:V2HI 2 "register_operand" "d")]
		       UNSPEC_MULEU_S_PH_QBR))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBR))
     (clobber (match_scratch:DI 3 "=x"))])]
  "TARGET_DSP"
  "muleu_s.ph.qbr\t%0,%1,%2"
  [(set_attr "type"	"imul3")
   (set_attr "mode"	"SI")])

;; MULQ*
(define_insn "mips_mulq_rs_ph"
  [(parallel
    [(set (match_operand:V2HI 0 "register_operand" "=d")
	  (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d")
			(match_operand:V2HI 2 "register_operand" "d")]
		       UNSPEC_MULQ_RS_PH))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH))
     (clobber (match_scratch:DI 3 "=x"))])]
  "TARGET_DSP"
  "mulq_rs.ph\t%0,%1,%2"
  [(set_attr "type"	"imul3")
   (set_attr "mode"	"SI")])

;; MULEQ*
(define_insn "mips_muleq_s_w_phl"
  [(parallel
    [(set (match_operand:SI 0 "register_operand" "=d")
	  (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")
		      (match_operand:V2HI 2 "register_operand" "d")]
		     UNSPEC_MULEQ_S_W_PHL))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHL))
     (clobber (match_scratch:DI 3 "=x"))])]
  "TARGET_DSP"
  "muleq_s.w.phl\t%0,%1,%2"
  [(set_attr "type"	"imul3")
   (set_attr "mode"	"SI")])

(define_insn "mips_muleq_s_w_phr"
  [(parallel
    [(set (match_operand:SI 0 "register_operand" "=d")
	  (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")
		      (match_operand:V2HI 2 "register_operand" "d")]
		     UNSPEC_MULEQ_S_W_PHR))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHR))
     (clobber (match_scratch:DI 3 "=x"))])]
  "TARGET_DSP"
  "muleq_s.w.phr\t%0,%1,%2"
  [(set_attr "type"	"imul3")
   (set_attr "mode"	"SI")])

;; DPAU*
(define_insn "mips_dpau_h_qbl"
  [(set (match_operand:DI 0 "register_operand" "=a")
	(unspec:DI [(match_operand:DI 1 "register_operand" "0")
		    (match_operand:V4QI 2 "register_operand" "d")
		    (match_operand:V4QI 3 "register_operand" "d")]
		   UNSPEC_DPAU_H_QBL))]
  "TARGET_DSP && !TARGET_64BIT"
  "dpau.h.qbl\t%q0,%2,%3"
  [(set_attr "type"	"imadd")
   (set_attr "mode"	"SI")])

(define_insn "mips_dpau_h_qbr"
  [(set (match_operand:DI 0 "register_operand" "=a")
	(unspec:DI [(match_operand:DI 1 "register_operand" "0")
		    (match_operand:V4QI 2 "register_operand" "d")
		    (match_operand:V4QI 3 "register_operand" "d")]
		   UNSPEC_DPAU_H_QBR))]
  "TARGET_DSP && !TARGET_64BIT"
  "dpau.h.qbr\t%q0,%2,%3"
  [(set_attr "type"	"imadd")
   (set_attr "mode"	"SI")])

;; DPSU*
(define_insn "mips_dpsu_h_qbl"
  [(set (match_operand:DI 0 "register_operand" "=a")
	(unspec:DI [(match_operand:DI 1 "register_operand" "0")
		    (match_operand:V4QI 2 "register_operand" "d")
		    (match_operand:V4QI 3 "register_operand" "d")]
		   UNSPEC_DPSU_H_QBL))]
  "TARGET_DSP && !TARGET_64BIT"
  "dpsu.h.qbl\t%q0,%2,%3"
  [(set_attr "type"	"imadd")
   (set_attr "mode"	"SI")])

(define_insn "mips_dpsu_h_qbr"
  [(set (match_operand:DI 0 "register_operand" "=a")
	(unspec:DI [(match_operand:DI 1 "register_operand" "0")
		    (match_operand:V4QI 2 "register_operand" "d")
		    (match_operand:V4QI 3 "register_operand" "d")]
		   UNSPEC_DPSU_H_QBR))]
  "TARGET_DSP && !TARGET_64BIT"
  "dpsu.h.qbr\t%q0,%2,%3"
  [(set_attr "type"	"imadd")
   (set_attr "mode"	"SI")])

;; DPAQ*
(define_insn "mips_dpaq_s_w_ph"
  [(parallel
    [(set (match_operand:DI 0 "register_operand" "=a")
	  (unspec:DI [(match_operand:DI 1 "register_operand" "0")
		      (match_operand:V2HI 2 "register_operand" "d")
		      (match_operand:V2HI 3 "register_operand" "d")]
		     UNSPEC_DPAQ_S_W_PH))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
			UNSPEC_DPAQ_S_W_PH))])]
  "TARGET_DSP && !TARGET_64BIT"
  "dpaq_s.w.ph\t%q0,%2,%3"
  [(set_attr "type"	"imadd")
   (set_attr "mode"	"SI")])

;; DPSQ*
(define_insn "mips_dpsq_s_w_ph"
  [(parallel
    [(set (match_operand:DI 0 "register_operand" "=a")
	  (unspec:DI [(match_operand:DI 1 "register_operand" "0")
		      (match_operand:V2HI 2 "register_operand" "d")
		      (match_operand:V2HI 3 "register_operand" "d")]
		     UNSPEC_DPSQ_S_W_PH))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
			UNSPEC_DPSQ_S_W_PH))])]
  "TARGET_DSP && !TARGET_64BIT"
  "dpsq_s.w.ph\t%q0,%2,%3"
  [(set_attr "type"	"imadd")
   (set_attr "mode"	"SI")])

;; MULSAQ*
(define_insn "mips_mulsaq_s_w_ph"
  [(parallel
    [(set (match_operand:DI 0 "register_operand" "=a")
	  (unspec:DI [(match_operand:DI 1 "register_operand" "0")
		      (match_operand:V2HI 2 "register_operand" "d")
		      (match_operand:V2HI 3 "register_operand" "d")]
		     UNSPEC_MULSAQ_S_W_PH))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
			UNSPEC_MULSAQ_S_W_PH))])]
  "TARGET_DSP && !TARGET_64BIT"
  "mulsaq_s.w.ph\t%q0,%2,%3"
  [(set_attr "type"	"imadd")
   (set_attr "mode"	"SI")])

;; DPAQ*
(define_insn "mips_dpaq_sa_l_w"
  [(parallel
    [(set (match_operand:DI 0 "register_operand" "=a")
	  (unspec:DI [(match_operand:DI 1 "register_operand" "0")
		      (match_operand:SI 2 "register_operand" "d")
		      (match_operand:SI 3 "register_operand" "d")]
		     UNSPEC_DPAQ_SA_L_W))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
			UNSPEC_DPAQ_SA_L_W))])]
  "TARGET_DSP && !TARGET_64BIT"
  "dpaq_sa.l.w\t%q0,%2,%3"
  [(set_attr "type"	"imadd")
   (set_attr "mode"	"SI")])

;; DPSQ*
(define_insn "mips_dpsq_sa_l_w"
  [(parallel
    [(set (match_operand:DI 0 "register_operand" "=a")
	  (unspec:DI [(match_operand:DI 1 "register_operand" "0")
		      (match_operand:SI 2 "register_operand" "d")
		      (match_operand:SI 3 "register_operand" "d")]
		     UNSPEC_DPSQ_SA_L_W))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
			UNSPEC_DPSQ_SA_L_W))])]
  "TARGET_DSP && !TARGET_64BIT"
  "dpsq_sa.l.w\t%q0,%2,%3"
  [(set_attr "type"	"imadd")
   (set_attr "mode"	"SI")])

;; MAQ*
(define_insn "mips_maq_s_w_phl"
  [(parallel
    [(set (match_operand:DI 0 "register_operand" "=a")
	  (unspec:DI [(match_operand:DI 1 "register_operand" "0")
		      (match_operand:V2HI 2 "register_operand" "d")
		      (match_operand:V2HI 3 "register_operand" "d")]
		     UNSPEC_MAQ_S_W_PHL))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
			UNSPEC_MAQ_S_W_PHL))])]
  "TARGET_DSP && !TARGET_64BIT"
  "maq_s.w.phl\t%q0,%2,%3"
  [(set_attr "type"	"imadd")
   (set_attr "mode"	"SI")])

(define_insn "mips_maq_s_w_phr"
  [(parallel
    [(set (match_operand:DI 0 "register_operand" "=a")
	  (unspec:DI [(match_operand:DI 1 "register_operand" "0")
		      (match_operand:V2HI 2 "register_operand" "d")
		      (match_operand:V2HI 3 "register_operand" "d")]
		     UNSPEC_MAQ_S_W_PHR))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
			UNSPEC_MAQ_S_W_PHR))])]
  "TARGET_DSP && !TARGET_64BIT"
  "maq_s.w.phr\t%q0,%2,%3"
  [(set_attr "type"	"imadd")
   (set_attr "mode"	"SI")])

;; MAQ_SA*
(define_insn "mips_maq_sa_w_phl"
  [(parallel
    [(set (match_operand:DI 0 "register_operand" "=a")
	  (unspec:DI [(match_operand:DI 1 "register_operand" "0")
		      (match_operand:V2HI 2 "register_operand" "d")
		      (match_operand:V2HI 3 "register_operand" "d")]
		     UNSPEC_MAQ_SA_W_PHL))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
			UNSPEC_MAQ_SA_W_PHL))])]
  "TARGET_DSP && !TARGET_64BIT"
  "maq_sa.w.phl\t%q0,%2,%3"
  [(set_attr "type"	"imadd")
   (set_attr "mode"	"SI")])

(define_insn "mips_maq_sa_w_phr"
  [(parallel
    [(set (match_operand:DI 0 "register_operand" "=a")
	  (unspec:DI [(match_operand:DI 1 "register_operand" "0")
		      (match_operand:V2HI 2 "register_operand" "d")
		      (match_operand:V2HI 3 "register_operand" "d")]
		     UNSPEC_MAQ_SA_W_PHR))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
			UNSPEC_MAQ_SA_W_PHR))])]
  "TARGET_DSP && !TARGET_64BIT"
  "maq_sa.w.phr\t%q0,%2,%3"
  [(set_attr "type"	"imadd")
   (set_attr "mode"	"SI")])

;; Table 2-4. MIPS DSP ASE Instructions: General Bit/Manipulation
;; BITREV
(define_insn "mips_bitrev"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(unspec:SI [(match_operand:SI 1 "register_operand" "d")]
		   UNSPEC_BITREV))]
  "TARGET_DSP"
  "bitrev\t%0,%1"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

;; INSV
(define_insn "mips_insv"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(unspec:SI [(match_operand:SI 1 "register_operand" "0")
		    (match_operand:SI 2 "register_operand" "d")
		    (reg:CCDSP CCDSP_SC_REGNUM)
		    (reg:CCDSP CCDSP_PO_REGNUM)]
		   UNSPEC_INSV))]
  "TARGET_DSP"
  "insv\t%0,%2"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

;; REPL*
(define_insn "mips_repl_qb"
  [(set (match_operand:V4QI 0 "register_operand" "=d,d")
	(unspec:V4QI [(match_operand:SI 1 "arith_operand" "I,d")]
		     UNSPEC_REPL_QB))]
  "TARGET_DSP"
{
  if (which_alternative == 0)
    {
      if (INTVAL (operands[1]) & ~(unsigned HOST_WIDE_INT) 0xff)
	operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
      return "repl.qb\t%0,%1";
    }
  return "replv.qb\t%0,%1";
}
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

(define_insn "mips_repl_ph"
  [(set (match_operand:V2HI 0 "register_operand" "=d,d")
	(unspec:V2HI [(match_operand:SI 1 "reg_imm10_operand" "YB,d")]
		     UNSPEC_REPL_PH))]
  "TARGET_DSP"