mips-dsp.md

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(define_constants
  [(CCDSP_PO_REGNUM	182)
   (CCDSP_SC_REGNUM	183)
   (CCDSP_CA_REGNUM	184)
   (CCDSP_OU_REGNUM	185)
   (CCDSP_CC_REGNUM	186)
   (CCDSP_EF_REGNUM	187)])

;; This mode macro allows si, v2hi, v4qi for all possible modes in DSP ASE.
(define_mode_macro DSP [(SI "TARGET_DSP")
			(V2HI "TARGET_DSP")
		 	(V4QI "TARGET_DSP")])

;; This mode macro allows v2hi, v4qi for vector/SIMD data.
(define_mode_macro DSPV [(V2HI "TARGET_DSP")
			 (V4QI "TARGET_DSP")])

;; This mode macro allows si, v2hi for Q31 and V2Q15 fixed-point data.
(define_mode_macro DSPQ [(SI "TARGET_DSP")
		         (V2HI "TARGET_DSP")])

;; DSP instructions use q for fixed-point data, and u for integer in the infix.
(define_mode_attr dspfmt1 [(SI "q") (V2HI "q") (V4QI "u")])

;; DSP instructions use nothing for fixed-point data, and u for integer in
;; the infix.
(define_mode_attr dspfmt1_1 [(SI "") (V2HI "") (V4QI "u")])

;; DSP instructions use w, ph, qb in the postfix.
(define_mode_attr dspfmt2 [(SI "w") (V2HI "ph") (V4QI "qb")])

;; DSP shift masks for SI, V2HI, V4QI.
(define_mode_attr dspshift_mask [(SI "0x1f") (V2HI "0xf") (V4QI "0x7")])

;; MIPS DSP ASE Revision 0.98 3/24/2005
;; Table 2-1. MIPS DSP ASE Instructions: Arithmetic
;; ADDQ*
(define_insn "add<DSPV:mode>3"
  [(parallel
    [(set (match_operand:DSPV 0 "register_operand" "=d")
	  (plus:DSPV (match_operand:DSPV 1 "register_operand" "d")
		     (match_operand:DSPV 2 "register_operand" "d")))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ))])]
  ""
  "add<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

(define_insn "mips_add<DSP:dspfmt1>_s_<DSP:dspfmt2>"
  [(parallel
    [(set (match_operand:DSP 0 "register_operand" "=d")
	  (unspec:DSP [(match_operand:DSP 1 "register_operand" "d")
		       (match_operand:DSP 2 "register_operand" "d")]
		      UNSPEC_ADDQ_S))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])]
  ""
  "add<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

;; SUBQ*
(define_insn "sub<DSPV:mode>3"
  [(parallel
    [(set (match_operand:DSPV 0 "register_operand" "=d")
	  (minus:DSPV (match_operand:DSPV 1 "register_operand" "d")
		      (match_operand:DSPV 2 "register_operand" "d")))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ))])]
  "TARGET_DSP"
  "sub<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

(define_insn "mips_sub<DSP:dspfmt1>_s_<DSP:dspfmt2>"
  [(parallel
    [(set (match_operand:DSP 0 "register_operand" "=d")
	  (unspec:DSP [(match_operand:DSP 1 "register_operand" "d")
		       (match_operand:DSP 2 "register_operand" "d")]
		      UNSPEC_SUBQ_S))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
  "TARGET_DSP"
  "sub<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

;; ADDSC
(define_insn "mips_addsc"
  [(parallel
    [(set (match_operand:SI 0 "register_operand" "=d")
	  (unspec:SI [(match_operand:SI 1 "register_operand" "d")
		      (match_operand:SI 2 "register_operand" "d")]
		     UNSPEC_ADDSC))
     (set (reg:CCDSP CCDSP_CA_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDSC))])]
  "TARGET_DSP"
  "addsc\t%0,%1,%2"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

;; ADDWC
(define_insn "mips_addwc"
  [(parallel
    [(set (match_operand:SI 0 "register_operand" "=d")
	  (unspec:SI [(match_operand:SI 1 "register_operand" "d")
		      (match_operand:SI 2 "register_operand" "d")
		    (reg:CCDSP CCDSP_CA_REGNUM)]
		     UNSPEC_ADDWC))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDWC))])]
  "TARGET_DSP"
  "addwc\t%0,%1,%2"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

;; MODSUB
(define_insn "mips_modsub"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(unspec:SI [(match_operand:SI 1 "register_operand" "d")
		    (match_operand:SI 2 "register_operand" "d")]
		   UNSPEC_MODSUB))]
  "TARGET_DSP"
  "modsub\t%0,%1,%2"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

;; RADDU*
(define_insn "mips_raddu_w_qb"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(unspec:SI [(match_operand:V4QI 1 "register_operand" "d")]
		   UNSPEC_RADDU_W_QB))]
  "TARGET_DSP"
  "raddu.w.qb\t%0,%1"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

;; ABSQ*
(define_insn "mips_absq_s_<DSPQ:dspfmt2>"
  [(parallel
    [(set (match_operand:DSPQ 0 "register_operand" "=d")
	  (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d")]
		       UNSPEC_ABSQ_S))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S))])]
  "TARGET_DSP"
  "absq_s.<DSPQ:dspfmt2>\t%0,%1"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

;; PRECRQ*
(define_insn "mips_precrq_qb_ph"
  [(set (match_operand:V4QI 0 "register_operand" "=d")
	(unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d")
		      (match_operand:V2HI 2 "register_operand" "d")]
		     UNSPEC_PRECRQ_QB_PH))]
  "TARGET_DSP"
  "precrq.qb.ph\t%0,%1,%2"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

(define_insn "mips_precrq_ph_w"
  [(set (match_operand:V2HI 0 "register_operand" "=d")
	(unspec:V2HI [(match_operand:SI 1 "register_operand" "d")
		      (match_operand:SI 2 "register_operand" "d")]
		     UNSPEC_PRECRQ_PH_W))]
  "TARGET_DSP"
  "precrq.ph.w\t%0,%1,%2"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

(define_insn "mips_precrq_rs_ph_w"
  [(parallel
    [(set (match_operand:V2HI 0 "register_operand" "=d")
	  (unspec:V2HI [(match_operand:SI 1 "register_operand" "d")
			(match_operand:SI 2 "register_operand" "d")]
		       UNSPEC_PRECRQ_RS_PH_W))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)]
			UNSPEC_PRECRQ_RS_PH_W))])]
  "TARGET_DSP"
  "precrq_rs.ph.w\t%0,%1,%2"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

;; PRECRQU*
(define_insn "mips_precrqu_s_qb_ph"
  [(parallel
    [(set (match_operand:V4QI 0 "register_operand" "=d")
	  (unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d")
			(match_operand:V2HI 2 "register_operand" "d")]
		       UNSPEC_PRECRQU_S_QB_PH))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)]
			UNSPEC_PRECRQU_S_QB_PH))])]
  "TARGET_DSP"
  "precrqu_s.qb.ph\t%0,%1,%2"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

;; PRECEQ*
(define_insn "mips_preceq_w_phl"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(unspec:SI [(match_operand:V2HI 1 "register_operand" "d")]
		   UNSPEC_PRECEQ_W_PHL))]
  "TARGET_DSP"
  "preceq.w.phl\t%0,%1"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

(define_insn "mips_preceq_w_phr"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(unspec:SI [(match_operand:V2HI 1 "register_operand" "d")]
		   UNSPEC_PRECEQ_W_PHR))]
  "TARGET_DSP"
  "preceq.w.phr\t%0,%1"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

;; PRECEQU*
(define_insn "mips_precequ_ph_qbl"
  [(set (match_operand:V2HI 0 "register_operand" "=d")
	(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
		     UNSPEC_PRECEQU_PH_QBL))]
  "TARGET_DSP"
  "precequ.ph.qbl\t%0,%1"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

(define_insn "mips_precequ_ph_qbr"
  [(set (match_operand:V2HI 0 "register_operand" "=d")
	(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
		     UNSPEC_PRECEQU_PH_QBR))]
  "TARGET_DSP"
  "precequ.ph.qbr\t%0,%1"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

(define_insn "mips_precequ_ph_qbla"
  [(set (match_operand:V2HI 0 "register_operand" "=d")
	(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
		     UNSPEC_PRECEQU_PH_QBLA))]
  "TARGET_DSP"
  "precequ.ph.qbla\t%0,%1"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

(define_insn "mips_precequ_ph_qbra"
  [(set (match_operand:V2HI 0 "register_operand" "=d")
	(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
		     UNSPEC_PRECEQU_PH_QBRA))]
  "TARGET_DSP"
  "precequ.ph.qbra\t%0,%1"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

;; PRECEU*
(define_insn "mips_preceu_ph_qbl"
  [(set (match_operand:V2HI 0 "register_operand" "=d")
	(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
		     UNSPEC_PRECEU_PH_QBL))]
  "TARGET_DSP"
  "preceu.ph.qbl\t%0,%1"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

(define_insn "mips_preceu_ph_qbr"
  [(set (match_operand:V2HI 0 "register_operand" "=d")
	(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
		     UNSPEC_PRECEU_PH_QBR))]
  "TARGET_DSP"
  "preceu.ph.qbr\t%0,%1"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

(define_insn "mips_preceu_ph_qbla"
  [(set (match_operand:V2HI 0 "register_operand" "=d")
	(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
		     UNSPEC_PRECEU_PH_QBLA))]
  "TARGET_DSP"
  "preceu.ph.qbla\t%0,%1"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

(define_insn "mips_preceu_ph_qbra"
  [(set (match_operand:V2HI 0 "register_operand" "=d")
	(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
		     UNSPEC_PRECEU_PH_QBRA))]
  "TARGET_DSP"
  "preceu.ph.qbra\t%0,%1"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

;; Table 2-2. MIPS DSP ASE Instructions: Shift
;; SHLL*
(define_insn "mips_shll_<DSPV:dspfmt2>"
  [(parallel
    [(set (match_operand:DSPV 0 "register_operand" "=d,d")
	  (unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d,d")
			(match_operand:SI 2 "arith_operand" "I,d")]
		       UNSPEC_SHLL))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL))])]
  "TARGET_DSP"
{
  if (which_alternative == 0)
    {
      if (INTVAL (operands[2])
	  & ~(unsigned HOST_WIDE_INT) <DSPV:dspshift_mask>)
	operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPV:dspshift_mask>);
      return "shll.<DSPV:dspfmt2>\t%0,%1,%2";
    }
  return "shllv.<DSPV:dspfmt2>\t%0,%1,%2";
}
  [(set_attr "type"	"shift")
   (set_attr "mode"	"SI")])

(define_insn "mips_shll_s_<DSPQ:dspfmt2>"
  [(parallel
    [(set (match_operand:DSPQ 0 "register_operand" "=d,d")
	  (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d")
			(match_operand:SI 2 "arith_operand" "I,d")]
		       UNSPEC_SHLL_S))
     (set (reg:CCDSP CCDSP_OU_REGNUM)
	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL_S))])]
  "TARGET_DSP"
{
  if (which_alternative == 0)
    {
      if (INTVAL (operands[2])
          & ~(unsigned HOST_WIDE_INT) <DSPQ:dspshift_mask>)
	operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPQ:dspshift_mask>);
      return "shll_s.<DSPQ:dspfmt2>\t%0,%1,%2";
    }
  return "shllv_s.<DSPQ:dspfmt2>\t%0,%1,%2";
}
  [(set_attr "type"	"shift")
   (set_attr "mode"	"SI")])

;; SHRL*
(define_insn "mips_shrl_qb"
  [(set (match_operand:V4QI 0 "register_operand" "=d,d")
	(unspec:V4QI [(match_operand:V4QI 1 "register_operand" "d,d")
		      (match_operand:SI 2 "arith_operand" "I,d")]
		     UNSPEC_SHRL_QB))]
  "TARGET_DSP"
{
  if (which_alternative == 0)
    {
      if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x7)
	operands[2] = GEN_INT (INTVAL (operands[2]) & 0x7);
      return "shrl.qb\t%0,%1,%2";