📄 mips.h
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/* Definitions of target machine for GNU compiler. MIPS version. Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. Contributed by A. Lichnewsky (lich@inria.inria.fr). Changed by Michael Meissner (meissner@osf.org). 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and Brendan Eich (brendan@microunity.com).This file is part of GCC.GCC is free software; you can redistribute it and/or modifyit under the terms of the GNU General Public License as published bythe Free Software Foundation; either version 2, or (at your option)any later version.GCC is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; without even the implied warranty ofMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See theGNU General Public License for more details.You should have received a copy of the GNU General Public Licensealong with GCC; see the file COPYING. If not, write tothe Free Software Foundation, 51 Franklin Street, Fifth Floor,Boston, MA 02110-1301, USA. *//* MIPS external variables defined in mips.c. *//* Which processor to schedule for. Since there is no difference between a R2000 and R3000 in terms of the scheduler, we collapse them into just an R3000. The elements of the enumeration must match exactly the cpu attribute in the mips.md machine description. */enum processor_type { PROCESSOR_R3000, PROCESSOR_4KC, PROCESSOR_4KP, PROCESSOR_5KC, PROCESSOR_5KF, PROCESSOR_20KC, PROCESSOR_24K, PROCESSOR_24KX, PROCESSOR_M4K, PROCESSOR_R3900, PROCESSOR_R6000, PROCESSOR_R4000, PROCESSOR_R4100, PROCESSOR_R4111, PROCESSOR_R4120, PROCESSOR_R4130, PROCESSOR_R4300, PROCESSOR_R4600, PROCESSOR_R4650, PROCESSOR_R5000, PROCESSOR_R5400, PROCESSOR_R5500, PROCESSOR_R7000, PROCESSOR_R8000, PROCESSOR_R9000, PROCESSOR_SB1, PROCESSOR_SR71000, PROCESSOR_MAX};/* Costs of various operations on the different architectures. */struct mips_rtx_cost_data{ unsigned short fp_add; unsigned short fp_mult_sf; unsigned short fp_mult_df; unsigned short fp_div_sf; unsigned short fp_div_df; unsigned short int_mult_si; unsigned short int_mult_di; unsigned short int_div_si; unsigned short int_div_di; unsigned short branch_cost; unsigned short memory_latency;};/* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */#define ABI_32 0#define ABI_N32 1#define ABI_64 2#define ABI_EABI 3#define ABI_O64 4/* Information about one recognized processor. Defined here for the benefit of TARGET_CPU_CPP_BUILTINS. */struct mips_cpu_info { /* The 'canonical' name of the processor as far as GCC is concerned. It's typically a manufacturer's prefix followed by a numerical designation. It should be lower case. */ const char *name; /* The internal processor number that most closely matches this entry. Several processors can have the same value, if there's no difference between them from GCC's point of view. */ enum processor_type cpu; /* The ISA level that the processor implements. */ int isa;};extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */extern const char *current_function_file; /* filename current function is in */extern int num_source_filenames; /* current .file # */extern int mips_section_threshold; /* # bytes of data/sdata cutoff */extern int sym_lineno; /* sgi next label # for each stmt */extern int set_noreorder; /* # of nested .set noreorder's */extern int set_nomacro; /* # of nested .set nomacro's */extern int set_noat; /* # of nested .set noat's */extern int set_volatile; /* # of nested .set volatile's */extern int mips_branch_likely; /* emit 'l' after br (branch likely) */extern int mips_dbx_regno[]; /* Map register # to debug register # */extern GTY(()) rtx cmp_operands[2];extern enum processor_type mips_arch; /* which cpu to codegen for */extern enum processor_type mips_tune; /* which cpu to schedule for */extern int mips_isa; /* architectural level */extern int mips_abi; /* which ABI to use */extern int mips16_hard_float; /* mips16 without -msoft-float */extern const struct mips_cpu_info mips_cpu_info_table[];extern const struct mips_cpu_info *mips_arch_info;extern const struct mips_cpu_info *mips_tune_info;extern const struct mips_rtx_cost_data *mips_cost;/* Macros to silence warnings about numbers being signed in traditional C and unsigned in ISO C when compiled on 32-bit hosts. */#define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */#define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */#define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */ /* Run-time compilation parameters selecting different hardware subsets. *//* True if the call patterns should be split into a jalr followed by an instruction to restore $gp. This is only ever true for SVR4 PIC, in which $gp is call-clobbered. It is only safe to split the load from the call when every use of $gp is explicit. */#define TARGET_SPLIT_CALLS \ (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)/* True if we can optimize sibling calls. For simplicity, we only handle cases in which call_insn_operand will reject invalid sibcall addresses. There are two cases in which this isn't true: - TARGET_MIPS16. call_insn_operand accepts constant addresses but there is no direct jump instruction. It isn't worth using sibling calls in this case anyway; they would usually be longer than normal calls. - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand accepts global constants, but "jr $25" is the only allowed sibcall. */#define TARGET_SIBCALLS \ (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))/* True if .gpword or .gpdword should be used for switch tables. Although GAS does understand .gpdword, the SGI linker mishandles the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64). We therefore disable GP-relative switch tables for n64 on IRIX targets. */#define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))/* Generate mips16 code */#define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)/* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */#define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)/* Generic ISA defines. */#define ISA_MIPS1 (mips_isa == 1)#define ISA_MIPS2 (mips_isa == 2)#define ISA_MIPS3 (mips_isa == 3)#define ISA_MIPS4 (mips_isa == 4)#define ISA_MIPS32 (mips_isa == 32)#define ISA_MIPS32R2 (mips_isa == 33)#define ISA_MIPS64 (mips_isa == 64)/* Architecture target defines. */#define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)#define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)#define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)#define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)#define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)#define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)#define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)#define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)#define TARGET_SB1 (mips_arch == PROCESSOR_SB1)#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)/* Scheduling target defines. */#define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)#define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)#define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)#define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)#define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)#define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)#define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)#define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)#define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)#define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)#define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)#define TUNE_SB1 (mips_tune == PROCESSOR_SB1)/* True if the pre-reload scheduler should try to create chains of multiply-add or multiply-subtract instructions. For example, suppose we have: t1 = a * b t2 = t1 + c * d t3 = e * f t4 = t3 - g * h t1 will have a higher priority than t2 and t3 will have a higher priority than t4. However, before reload, there is no dependence between t1 and t3, and they can often have similar priorities. The scheduler will then tend to prefer: t1 = a * b t3 = e * f t2 = t1 + c * d t4 = t3 - g * h which stops us from making full use of macc/madd-style instructions. This sort of situation occurs frequently in Fourier transforms and in unrolled loops. To counter this, the TUNE_MACC_CHAINS code will reorder the ready queue so that chained multiply-add and multiply-subtract instructions appear ahead of any other instruction that is likely to clobber lo. In the example above, if t2 and t3 become ready at the same time, the code ensures that t2 is scheduled first. Multiply-accumulate instructions are a bigger win for some targets than others, so this macro is defined on an opt-in basis. */#define TUNE_MACC_CHAINS (TUNE_MIPS5500 \ || TUNE_MIPS4120 \ || TUNE_MIPS4130)#define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)#define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)/* IRIX specific stuff. */#define TARGET_IRIX 0#define TARGET_IRIX6 0/* Define preprocessor macros for the -march and -mtune options. PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected processor. If INFO's canonical name is "foo", define PREFIX to be "foo", and define an additional macro PREFIX_FOO. */#define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \ do \ { \ char *macro, *p; \ \ macro = concat ((PREFIX), "_", (INFO)->name, NULL); \ for (p = macro; *p != 0; p++) \ *p = TOUPPER (*p); \ \ builtin_define (macro); \ builtin_define_with_value ((PREFIX), (INFO)->name, 1); \ free (macro); \ } \ while (0)/* Target CPU builtins. */#define TARGET_CPU_CPP_BUILTINS() \ do \ { \ /* Everyone but IRIX defines this to mips. */ \ if (!TARGET_IRIX) \ builtin_assert ("machine=mips"); \ \ builtin_assert ("cpu=mips"); \ builtin_define ("__mips__"); \ builtin_define ("_mips"); \ \ /* We do this here because __mips is defined below \ and so we can't use builtin_define_std. */ \ if (!flag_iso) \ builtin_define ("mips"); \ \ if (TARGET_64BIT) \ builtin_define ("__mips64"); \ \ if (!TARGET_IRIX) \ { \ /* Treat _R3000 and _R4000 like register-size \ defines, which is how they've historically \ been used. */ \ if (TARGET_64BIT) \ { \ builtin_define_std ("R4000"); \ builtin_define ("_R4000"); \ } \ else \ { \ builtin_define_std ("R3000"); \ builtin_define ("_R3000"); \ } \ } \ if (TARGET_FLOAT64) \ builtin_define ("__mips_fpr=64"); \ else \ builtin_define ("__mips_fpr=32"); \ \ if (TARGET_MIPS16) \ builtin_define ("__mips16"); \ \ if (TARGET_MIPS3D) \ builtin_define ("__mips3d"); \ \ if (TARGET_DSP) \ builtin_define ("__mips_dsp"); \ \ MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \ MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \ \ if (ISA_MIPS1) \ { \ builtin_define ("__mips=1"); \ builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \ } \ else if (ISA_MIPS2) \ { \ builtin_define ("__mips=2"); \ builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \ } \ else if (ISA_MIPS3) \ { \ builtin_define ("__mips=3"); \ builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \ } \ else if (ISA_MIPS4) \ { \ builtin_define ("__mips=4"); \ builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \⌨️ 快捷键说明
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