crt1.asm

linux下编程用 编译软件

/* Copyright (C) 2000, 2001, 2003, 2004, 2005 Free Software Foundation, Inc.
   This file was pretty much copied from newlib.

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.

In addition to the permissions in the GNU General Public License, the
Free Software Foundation gives you unlimited permission to link the
compiled version of this file into combinations with other programs,
and to distribute those combinations without any restriction coming
from the use of this file.  (The General Public License restrictions
do apply in other respects; for example, they cover modification of
the file, and distribution when not linked into a combine
executable.)

GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; see the file COPYING.  If not, write to
the Free Software Foundation, 51 Franklin Street, Fifth Floor,
Boston, MA 02110-1301, USA.  */

#ifdef MMU_SUPPORT
	/* Section used for exception/timer interrupt stack area */
	.section .data.vbr.stack,"aw"
	.align 4
	.global __ST_VBR
__ST_VBR:
	.zero 1024 * 2          /* ; 2k for VBR handlers */
/* Label at the highest stack address where the stack grows from */
__timer_stack:
#endif /* MMU_SUPPORT */
	
	/* ;----------------------------------------
	Normal newlib crt1.asm */

#ifdef __SH5__
	.section .data,"aw"
	.global ___data
___data:

	.section .rodata,"a"
	.global ___rodata
___rodata:

#define ICCR_BASE  0x01600000
#define OCCR_BASE  0x01e00000
#define MMUIR_BASE 0x00000000
#define MMUDR_BASE 0x00800000

#define PTE_ENABLED     1
#define PTE_DISABLED    0

#define PTE_SHARED (1 << 1)
#define PTE_NOT_SHARED  0

#define PTE_CB_UNCACHEABLE  0
#define PTE_CB_DEVICE       1
#define PTE_CB_CACHEABLE_WB 2
#define PTE_CB_CACHEABLE_WT 3

#define PTE_SZ_4KB   (0 << 3)
#define PTE_SZ_64KB  (1 << 3)
#define PTE_SZ_1MB   (2 << 3)
#define PTE_SZ_512MB (3 << 3)

#define PTE_PRR      (1 << 6)
#define PTE_PRX      (1 << 7)
#define PTE_PRW      (1 << 8)
#define PTE_PRU      (1 << 9)

#define SR_MMU_BIT          31
#define SR_BL_BIT           28

#define ALIGN_4KB  (0xfff)
#define ALIGN_1MB  (0xfffff)
#define ALIGN_512MB (0x1fffffff)

#define DYNACON_BASE               0x0f000000
#define DM_CB_DLINK_BASE           0x0c000000
#define DM_DB_DLINK_BASE           0x0b000000

#define FEMI_AREA_0                0x00000000
#define FEMI_AREA_1                0x04000000
#define FEMI_AREA_2                0x05000000
#define FEMI_AREA_3                0x06000000
#define FEMI_AREA_4                0x07000000
#define FEMI_CB                    0x08000000

#define EMI_BASE                   0X80000000

#define DMA_BASE                   0X0e000000

#define CPU_BASE                   0X0d000000

#define PERIPH_BASE                0X09000000
#define DMAC_BASE                  0x0e000000
#define INTC_BASE                  0x0a000000
#define CPRC_BASE                  0x0a010000
#define TMU_BASE                   0x0a020000
#define SCIF_BASE                  0x0a030000
#define RTC_BASE                   0x0a040000



#define LOAD_CONST32(val, reg) \
	movi	((val) >> 16) & 65535, reg; \
	shori	(val) & 65535, reg

#define LOAD_PTEH_VAL(sym, align, bits, scratch_reg, reg) \
	LOAD_ADDR (sym, reg); \
	LOAD_CONST32 ((align), scratch_reg); \
	andc	reg, scratch_reg, reg; \
	LOAD_CONST32 ((bits), scratch_reg); \
	or	reg, scratch_reg, reg

#define LOAD_PTEL_VAL(sym, align, bits, scratch_reg, reg) \
	LOAD_ADDR (sym, reg); \
	LOAD_CONST32 ((align), scratch_reg); \
	andc	reg, scratch_reg, reg; \
	LOAD_CONST32 ((bits), scratch_reg); \
	or	reg, scratch_reg, reg

#define SET_PTE(pte_addr_reg, pteh_val_reg, ptel_val_reg) \
	putcfg  pte_addr_reg, 0, r63; \
	putcfg  pte_addr_reg, 1, ptel_val_reg; \
	putcfg  pte_addr_reg, 0, pteh_val_reg

#if __SH5__ == 64
	.section .text,"ax"
#define LOAD_ADDR(sym, reg) \
	movi	(sym >> 48) & 65535, reg; \
	shori	(sym >> 32) & 65535, reg; \
	shori	(sym >> 16) & 65535, reg; \
	shori	sym & 65535, reg
#else
	.mode	SHmedia
	.section .text..SHmedia32,"ax"
#define LOAD_ADDR(sym, reg) \
	movi	(sym >> 16) & 65535, reg; \
	shori	sym & 65535, reg
#endif
	.global start
start:
	LOAD_ADDR (_stack, r15)

#ifdef MMU_SUPPORT
	! Set up the VM using the MMU and caches

	! .vm_ep is first instruction to execute
	! after VM initialization
	pt/l	.vm_ep, tr1
	
	! Configure instruction cache (ICCR)
	movi	3, r2
	movi	0, r3
	LOAD_ADDR (ICCR_BASE, r1)
	putcfg	r1, 0, r2
	putcfg	r1, 1, r3

	! movi	7, r2 ! write through
	! Configure operand cache (OCCR)
	LOAD_ADDR (OCCR_BASE, r1)
	putcfg	r1, 0, r2
	putcfg	r1, 1, r3

	! Disable all PTE translations
	LOAD_ADDR (MMUIR_BASE, r1)
	LOAD_ADDR (MMUDR_BASE, r2)
	movi	64, r3
	pt/l	.disable_ptes_loop, tr0
.disable_ptes_loop:
	putcfg	r1, 0, r63
	putcfg	r2, 0, r63
	addi	r1, 16, r1
	addi	r2, 16, r2
	addi	r3, -1, r3
	bgt	r3, r63, tr0

	LOAD_ADDR (MMUIR_BASE, r1)

	! FEMI instruction mappings
	!   Area 0 - 1Mb cacheable at 0x00000000
	!   Area 1 - None
	!   Area 2 - 1Mb cacheable at 0x05000000
	!          - 1Mb cacheable at 0x05100000
	!   Area 3 - None
	!   Area 4 - None

	! Map a 1Mb page for instructions at 0x00000000
	LOAD_PTEH_VAL (FEMI_AREA_0, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL (FEMI_AREA_0, ALIGN_1MB, PTE_CB_CACHEABLE_WB | PTE_SZ_1MB | PTE_PRX | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	! Map a 1Mb page for instructions at 0x05000000
	addi	r1, 16, r1
	LOAD_PTEH_VAL (FEMI_AREA_2, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL (FEMI_AREA_2, ALIGN_1MB, PTE_CB_CACHEABLE_WB | PTE_SZ_1MB | PTE_PRX | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	! Map a 1Mb page for instructions at 0x05100000
	addi	r1, 16, r1
	LOAD_PTEH_VAL ((FEMI_AREA_2+0x100000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL ((FEMI_AREA_2+0x100000), ALIGN_1MB, PTE_CB_CACHEABLE_WB | PTE_SZ_1MB | PTE_PRX | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	! Map a 512M page for instructions at EMI base
	addi	r1, 16, r1
	LOAD_PTEH_VAL (EMI_BASE, ALIGN_512MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL (EMI_BASE, ALIGN_512MB, PTE_CB_CACHEABLE_WB | PTE_SZ_512MB | PTE_PRX | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	! Map a 4K page for instructions at DM_DB_DLINK_BASE
	addi	r1, 16, r1
	LOAD_PTEH_VAL (DM_DB_DLINK_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL (DM_DB_DLINK_BASE, ALIGN_4KB, PTE_CB_CACHEABLE_WB | PTE_SZ_4KB | PTE_PRX | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	LOAD_ADDR (MMUDR_BASE, r1)

	! FEMI data mappings
	!   Area 0 - 1Mb cacheable at 0x00000000
	!   Area 1 - 1Mb device at 0x04000000
	!   Area 2 - 1Mb cacheable at 0x05000000
	!          - 1Mb cacheable at 0x05100000
	!   Area 3 - None
	!   Area 4 - None
	!   CB     - 1Mb device at 0x08000000

	! Map a 1Mb page for data at 0x00000000
	LOAD_PTEH_VAL (FEMI_AREA_0, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL (FEMI_AREA_0, ALIGN_1MB, PTE_CB_CACHEABLE_WB | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	! Map a 1Mb page for data at 0x04000000
	addi	r1, 16, r1
	LOAD_PTEH_VAL (FEMI_AREA_1, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL (FEMI_AREA_1, ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	! Map a 1Mb page for data at 0x05000000
	addi	r1, 16, r1
	LOAD_PTEH_VAL (FEMI_AREA_2, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL (FEMI_AREA_2, ALIGN_1MB, PTE_CB_CACHEABLE_WB | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	! Map a 1Mb page for data at 0x05100000
	addi	r1, 16, r1
	LOAD_PTEH_VAL ((FEMI_AREA_2+0x100000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL ((FEMI_AREA_2+0x100000), ALIGN_1MB, PTE_CB_CACHEABLE_WB | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	! Map a 4K page for registers at 0x08000000
	addi	r1, 16, r1
	LOAD_PTEH_VAL (FEMI_CB, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL (FEMI_CB, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	! Map a 512M page for data at EMI
	addi	r1, 16, r1
	LOAD_PTEH_VAL (EMI_BASE, ALIGN_512MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL (EMI_BASE, ALIGN_512MB, PTE_CB_CACHEABLE_WB | PTE_SZ_512MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	! Map a 4K page for DYNACON at DYNACON_BASE
	addi	r1, 16, r1
	LOAD_PTEH_VAL (DYNACON_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL (DYNACON_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	! Map a 4K page for instructions at DM_DB_DLINK_BASE
	addi	r1, 16, r1
	LOAD_PTEH_VAL (DM_DB_DLINK_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL (DM_DB_DLINK_BASE, ALIGN_4KB, PTE_CB_CACHEABLE_WB | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	! Map a 4K page for data at DM_DB_DLINK_BASE+0x1000
	addi	r1, 16, r1
	LOAD_PTEH_VAL ((DM_DB_DLINK_BASE+0x1000), ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL ((DM_DB_DLINK_BASE+0x1000), ALIGN_4KB, PTE_CB_UNCACHEABLE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	! Map a 4K page for stack DM_DB_DLINK_BASE+0x2000
	addi	r1, 16, r1
	LOAD_PTEH_VAL ((DM_DB_DLINK_BASE+0x2000), ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL ((DM_DB_DLINK_BASE+0x2000), ALIGN_4KB, PTE_CB_CACHEABLE_WB | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	! Map a 1M page for DM_CB_BASE2 at DM_CB_DLINK 
	! 0x0c000000 - 0x0c0fffff
	addi	r1, 16, r1
	LOAD_PTEH_VAL (DM_CB_DLINK_BASE, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL (DM_CB_DLINK_BASE, ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	! Map a 1M page for DM_CB_BASE2 at DM_CB_DLINK 
	! 0x0c100000 - 0x0c1fffff
	addi	r1, 16, r1
	LOAD_PTEH_VAL ((DM_CB_DLINK_BASE+0x100000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL ((DM_CB_DLINK_BASE+0x100000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	! Map a 1M page for DM_CB_BASE2 at DM_CB_DLINK 
	! 0x0c200000 - 0x0c2fffff
	addi	r1, 16, r1
	LOAD_PTEH_VAL ((DM_CB_DLINK_BASE+0x200000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL ((DM_CB_DLINK_BASE+0x200000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	! Map a 1M page for DM_CB_BASE2 at DM_CB_DLINK 
	! 0x0c400000 - 0x0c4fffff
	addi	r1, 16, r1
	LOAD_PTEH_VAL ((DM_CB_DLINK_BASE+0x400000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL ((DM_CB_DLINK_BASE+0x400000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	! Map a 1M page for DM_CB_BASE2 at DM_CB_DLINK 
	! 0x0c800000 - 0x0c8fffff
	addi	r1, 16, r1
	LOAD_PTEH_VAL ((DM_CB_DLINK_BASE+0x800000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL ((DM_CB_DLINK_BASE+0x800000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	! Map a 4K page for DMA control registers
	addi	r1, 16, r1
	LOAD_PTEH_VAL (DMA_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL (DMA_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	! Map lots of 4K pages for peripherals

	! /* peripheral */
	addi	r1, 16, r1
	LOAD_PTEH_VAL (PERIPH_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL (PERIPH_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)
	! /* dmac */
	addi	r1, 16, r1
	LOAD_PTEH_VAL (DMAC_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL (DMAC_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)
	! /* intc */
	addi	r1, 16, r1
	LOAD_PTEH_VAL (INTC_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL (INTC_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)
	! /* rtc */
	addi	r1, 16, r1
	LOAD_PTEH_VAL (RTC_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL (RTC_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)
	! /* dmac */
	addi	r1, 16, r1
	LOAD_PTEH_VAL (TMU_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL (TMU_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)
	! /* scif */
	addi	r1, 16, r1
	LOAD_PTEH_VAL (SCIF_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL (SCIF_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)
	! /* cprc */
	addi	r1, 16, r1
	LOAD_PTEH_VAL (CPRC_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL (CPRC_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	! Map CPU WPC registers 
	addi	r1, 16, r1
	LOAD_PTEH_VAL (CPU_BASE, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL (CPU_BASE, ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)
	addi	r1, 16, r1

	LOAD_PTEH_VAL ((CPU_BASE+0x100000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL ((CPU_BASE+0x100000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	addi	r1, 16, r1
	LOAD_PTEH_VAL ((CPU_BASE+0x200000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL ((CPU_BASE+0x200000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	addi	r1, 16, r1
	LOAD_PTEH_VAL ((CPU_BASE+0x400000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
	LOAD_PTEL_VAL ((CPU_BASE+0x400000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
	SET_PTE (r1, r2, r3)

	! Switch over to virtual addressing and enabled cache
	getcon	sr, r1
	movi	1, r2
	shlli	r2, SR_BL_BIT, r2
	or	r1, r2, r1
	putcon	r1, ssr
	getcon	sr, r1
	movi	1, r2
	shlli	r2, SR_MMU_BIT, r2
	or	r1, r2, r1
	putcon	r1, ssr
	gettr	tr1, r1
	putcon	r1, spc
	synco
	rte

	! VM entry point.  From now on, we are in VM mode.
.vm_ep:

	! Install the trap handler, by seeding vbr with the
	! correct value, and by assigning sr.bl = 0.

	LOAD_ADDR (vbr_start, r1)
	putcon	r1, vbr
	movi	~(1<<28), r1
	getcon	sr, r2
	and     r1, r2, r2
	putcon	r2, sr
#endif /* MMU_SUPPORT */

	pt/l	.Lzero_bss_loop, tr0
	pt/l	_init, tr5
	pt/l	___setup_argv_and_call_main, tr6
	pt/l	_exit, tr7

	! zero out bss
	LOAD_ADDR (_edata, r0)
	LOAD_ADDR (_end, r1)
.Lzero_bss_loop:
	stx.q	r0, r63, r63
	addi	r0, 8, r0
	bgt/l	r1, r0, tr0

	LOAD_ADDR (___data, r26)
	LOAD_ADDR (___rodata, r27)

#ifdef __SH_FPU_ANY__
	getcon	sr, r0
	! enable the FP unit, by resetting SR.FD
	! also zero out SR.FR, SR.SZ and SR.PR, as mandated by the ABI
	movi	0, r1
	shori	0xf000, r1
	andc	r0, r1, r0
	putcon	r0, sr
#if __SH5__ == 32
	pt/l ___set_fpscr, tr0
	movi	0, r4
	blink	tr0, r18
#endif
#endif

	! arrange for exit to call fini
	pt/l	_atexit, tr1
	LOAD_ADDR (_fini, r2)
	blink	tr1, r18

	! call init
	blink	tr5, r18

	! call the mainline
	blink	tr6, r18

	! call exit
	blink	tr7, r18
	! We should never return from _exit but in case we do we would enter the
	! the following tight loop. This avoids executing any data that might follow.
limbo:
	pt/l limbo, tr0
	blink tr0, r63
	
#ifdef MMU_SUPPORT
	! All these traps are handled in the same place. 
	.balign 256
vbr_start:
	pt/l handler, tr0	! tr0 trashed.
	blink tr0, r63
	.balign 256
vbr_100:
	pt/l handler, tr0	! tr0 trashed.
	blink tr0, r63
vbr_100_end:
	.balign 256
vbr_200:
	pt/l handler, tr0	! tr0 trashed.
	blink tr0, r63
	.balign 256
vbr_300:
	pt/l handler, tr0	! tr0 trashed.
	blink tr0, r63
	.balign 256	
vbr_400:	! Should be at vbr+0x400
handler:
	/* If the trap handler is there call it */
	LOAD_ADDR (__superh_trap_handler, r2)
	pta chandler,tr2
	beq r2, r63, tr2 /* If zero, ie not present branch around to chandler */
	/* Now call the trap handler with as much of the context unchanged as possible.
	   Move trapping address into R18 to make it look like the trap point */
	getcon spc, r18
	pt/l __superh_trap_handler, tr0
	blink tr0, r7
chandler:	
	getcon	spc, r62
	getcon expevt, r2
	pt/l	_exit, tr0
	blink	tr0, r63

	/* Simulated trap handler */
	.section	.text..SHmedia32,"ax"
gcc2_compiled.:
	.section	.debug_abbrev
.Ldebug_abbrev0:
	.section	.text..SHmedia32
.Ltext0:
	.section	.debug_info
.Ldebug_info0:
	.section	.debug_line
.Ldebug_line0:
	.section	.text..SHmedia32,"ax"
	.align 5
	.global	__superh_trap_handler
	.type	__superh_trap_handler,@function
__superh_trap_handler:
.LFB1:
	ptabs	r18, tr0
	addi.l	r15, -8, r15
	st.l	r15, 4, r14
	addi.l	r15, -8, r15
	add.l	r15, r63, r14
	st.l	r14, 0, r2
	 ptabs r7, tr0 
	addi.l	r14, 8, r14
	add.l	r14, r63, r15
	ld.l	r15, 4, r14
	addi.l	r15, 8, r15
	blink	tr0, r63
.LFE1:
.Lfe1:
	.size	__superh_trap_handler,.Lfe1-__superh_trap_handler

	.section	.text..SHmedia32
.Letext0:

	.section	.debug_info
	.ualong	0xa7
	.uaword	0x2
	.ualong	.Ldebug_abbrev0
	.byte	0x4
	.byte	0x1
	.ualong	.Ldebug_line0
	.ualong	.Letext0
	.ualong	.Ltext0
	.string	"trap_handler.c"

	.string	"xxxxxxxxxxxxxxxxxxxxxxxxxxxx"

	.string	"GNU C 2.97-sh5-010522"

	.byte	0x1
	.byte	0x2
	.ualong	0x9a
	.byte	0x1
	.string	"_superh_trap_handler"

	.byte	0x1
	.byte	0x2
	.byte	0x1
	.ualong	.LFB1
	.ualong	.LFE1
	.byte	0x1
	.byte	0x5e
	.byte	0x3
	.string	"trap_reason"

	.byte	0x1
	.byte	0x1
	.ualong	0x9a
	.byte	0x2
	.byte	0x91
	.byte	0x0
	.byte	0x0
	.byte	0x4
	.string	"unsigned int"

	.byte	0x4
	.byte	0x7
	.byte	0x0

	.section	.debug_abbrev
	.byte	0x1
	.byte	0x11
	.byte	0x1
	.byte	0x10
	.byte	0x6
	.byte	0x12
	.byte	0x1
	.byte	0x11
	.byte	0x1
	.byte	0x3
	.byte	0x8
	.byte	0x1b
	.byte	0x8
	.byte	0x25
	.byte	0x8
	.byte	0x13
	.byte	0xb
	.byte	0,0
	.byte	0x2
	.byte	0x2e
	.byte	0x1