sh.h

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  FPSCR_REGS,
  GENERAL_FP_REGS,
  GENERAL_DF_REGS,
  TARGET_REGS,
  ALL_REGS,
  LIM_REG_CLASSES
};

#define N_REG_CLASSES  (int) LIM_REG_CLASSES

/* Give names of register classes as strings for dump file.  */
#define REG_CLASS_NAMES	\
{			\
  "NO_REGS",		\
  "R0_REGS",		\
  "PR_REGS",		\
  "T_REGS",		\
  "MAC_REGS",		\
  "FPUL_REGS",		\
  "SIBCALL_REGS",	\
  "GENERAL_REGS",	\
  "FP0_REGS",		\
  "FP_REGS",		\
  "DF_HI_REGS",		\
  "DF_REGS",		\
  "FPSCR_REGS",		\
  "GENERAL_FP_REGS",	\
  "GENERAL_DF_REGS",	\
  "TARGET_REGS",	\
  "ALL_REGS",		\
}

/* Define which registers fit in which classes.
   This is an initializer for a vector of HARD_REG_SET
   of length N_REG_CLASSES.  */

#define REG_CLASS_CONTENTS						\
{									\
/* NO_REGS:  */								\
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	\
/* R0_REGS:  */								\
  { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	\
/* PR_REGS:  */								\
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 },	\
/* T_REGS:  */								\
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 },	\
/* MAC_REGS:  */							\
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 },	\
/* FPUL_REGS:  */							\
  { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 },	\
/* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE.  */	\
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	\
/* GENERAL_REGS:  */							\
  { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 },	\
/* FP0_REGS:  */							\
  { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 },	\
/* FP_REGS:  */								\
  { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 },	\
/* DF_HI_REGS:  Initialized in CONDITIONAL_REGISTER_USAGE.  */		\
  { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 },	\
/* DF_REGS:  */								\
  { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 },	\
/* FPSCR_REGS:  */							\
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 },	\
/* GENERAL_FP_REGS:  */							\
  { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 },	\
/* GENERAL_DF_REGS:  */							\
  { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 },	\
/* TARGET_REGS:  */							\
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff },	\
/* ALL_REGS:  */							\
  { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff },	\
}

/* The same information, inverted:
   Return the class number of the smallest class containing
   reg number REGNO.  This could be a conditional expression
   or could index an array.  */

extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
#define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]

/* When defined, the compiler allows registers explicitly used in the
   rtl to be used as spill registers but prevents the compiler from
   extending the lifetime of these registers.  */

#define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)

/* The order in which register should be allocated.  */
/* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
   and GENERAL_FP_REGS the alternate class.  Since FP0 is likely to be
   spilled or used otherwise, we better have the FP_REGS allocated first.  */
#define REG_ALLOC_ORDER \
  {/* Caller-saved FPRs */ \
    65, 66, 67, 68, 69, 70, 71, 64, \
    72, 73, 74, 75, 80, 81, 82, 83, \
    84, 85, 86, 87, 88, 89, 90, 91, \
    92, 93, 94, 95, 96, 97, 98, 99, \
   /* Callee-saved FPRs */ \
    76, 77, 78, 79,100,101,102,103, \
   104,105,106,107,108,109,110,111, \
   112,113,114,115,116,117,118,119, \
   120,121,122,123,124,125,126,127, \
   136,137,138,139,140,141,142,143, \
   /* FPSCR */ 151, \
   /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
     1,  2,  3,  7,  6,  5,  4,  0, \
     8,  9, 17, 19, 20, 21, 22, 23, \
    36, 37, 38, 39, 40, 41, 42, 43, \
    60, 61, 62, \
   /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
    10, 11, 12, 13, 14, 18, \
    /* SH5 callee-saved GPRs */ \
    28, 29, 30, 31, 32, 33, 34, 35, \
    44, 45, 46, 47, 48, 49, 50, 51, \
    52, 53, 54, 55, 56, 57, 58, 59, \
   /* FPUL */ 150, \
   /* SH5 branch target registers */ \
   128,129,130,131,132,133,134,135, \
   /* Fixed registers */ \
    15, 16, 24, 25, 26, 27, 63,144, \
   145,146,147,148,149,152,153 }

/* The class value for index registers, and the one for base regs.  */
#define INDEX_REG_CLASS \
  (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
#define BASE_REG_CLASS	 GENERAL_REGS

/* Get reg_class from a letter such as appears in the machine
   description.  */
extern enum reg_class reg_class_from_letter[];

/* We might use 'Rxx' constraints in the future for exotic reg classes.*/
#define REG_CLASS_FROM_CONSTRAINT(C, STR) \
  (ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS )

/* Overview of uppercase letter constraints:
   A: Addresses (constraint len == 3)
    Ac4: sh4 cache operations
    Ac5: sh5 cache operations
   Bxx: miscellaneous constraints
    Bsc: SCRATCH - for the scratch register in movsi_ie in the
	 fldi0 / fldi0 cases
   C: Constants other than only CONST_INT (constraint len == 3)
    C16: 16 bit constant, literal or symbolic
    Csy: label or symbol
    Cpg: non-explicit constants that can be directly loaded into a general
	 purpose register in PIC code.  like 's' except we don't allow
	 PIC_DIRECT_ADDR_P
   IJKLMNOP: CONT_INT constants
    Ixx: signed xx bit
    J16: 0xffffffff00000000 | 0x00000000ffffffff
    Kxx: unsigned xx bit
    M: 1
    N: 0
    P27: 1 | 2 | 8 | 16
   Q: pc relative load operand
   Rxx: reserved for exotic register classes.
   S: extra memory (storage) constraints (constraint len == 3)
    Sua: unaligned memory operations
   W: vector
   Z: zero in any mode

   unused CONST_INT constraint letters: LO
   unused EXTRA_CONSTRAINT letters: D T U Y */

#define CONSTRAINT_LEN(C,STR) \
  (((C) == 'A' || (C) == 'B' || (C) == 'C' \
    || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
    || (C) == 'R' || (C) == 'S') \
   ? 3 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))

/* The letters I, J, K, L and M in a register constraint string
   can be used to stand for particular ranges of immediate operands.
   This macro defines what the ranges are.
   C is the letter, and VALUE is a constant value.
   Return 1 if VALUE is in the range specified by C.
	I08: arithmetic operand -127..128, as used in add, sub, etc
	I16: arithmetic operand -32768..32767, as used in SHmedia movi and shori
	P27: shift operand 1,2,8 or 16
	K08: logical operand 0..255, as used in and, or, etc.
	M: constant 1
	N: constant 0
	I06: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
	I10: arithmetic operand -512..511, as used in SHmedia andi, ori
*/

#define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
				 && ((HOST_WIDE_INT)(VALUE)) <= 31)
#define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
				 && ((HOST_WIDE_INT)(VALUE)) <= 127)
#define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
				 && ((HOST_WIDE_INT)(VALUE)) <= 511)
#define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
				 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
#define CONST_OK_FOR_I20(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -524288 \
				 && ((HOST_WIDE_INT)(VALUE)) <= 524287 \
				 && TARGET_SH2A)
#define CONST_OK_FOR_I(VALUE, STR) \
  ((STR)[1] == '0' && (STR)[2] == '6' ? CONST_OK_FOR_I06 (VALUE) \
   : (STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_I08 (VALUE) \
   : (STR)[1] == '1' && (STR)[2] == '0' ? CONST_OK_FOR_I10 (VALUE) \
   : (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_I16 (VALUE) \
   : (STR)[1] == '2' && (STR)[2] == '0' ? CONST_OK_FOR_I20 (VALUE) \
   : 0)

#define CONST_OK_FOR_J16(VALUE) \
  ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
   || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
#define CONST_OK_FOR_J(VALUE, STR) \
  ((STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_J16 (VALUE) \
   : 0)

#define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
				 && ((HOST_WIDE_INT)(VALUE)) <= 255)
#define CONST_OK_FOR_K(VALUE, STR) \
  ((STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_K08 (VALUE) \
   : 0)
#define CONST_OK_FOR_P27(VALUE) \
  ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
#define CONST_OK_FOR_P(VALUE, STR) \
  ((STR)[1] == '2' && (STR)[2] == '7' ? CONST_OK_FOR_P27 (VALUE) \
   : 0)
#define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
#define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
#define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR)	\
     ((C) == 'I' ? CONST_OK_FOR_I ((VALUE), (STR))	\
    : (C) == 'J' ? CONST_OK_FOR_J ((VALUE), (STR))	\
    : (C) == 'K' ? CONST_OK_FOR_K ((VALUE), (STR))	\
    : (C) == 'M' ? CONST_OK_FOR_M (VALUE)		\
    : (C) == 'N' ? CONST_OK_FOR_N (VALUE)		\
    : (C) == 'P' ? CONST_OK_FOR_P ((VALUE), (STR))	\
    : 0)

/* Similar, but for floating constants, and defining letters G and H.
   Here VALUE is the CONST_DOUBLE rtx itself.  */

#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)		\
((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ())	\
 : (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ())	\
 : (C) == 'F')

/* Given an rtx X being reloaded into a reg required to be
   in class CLASS, return the class of reg to actually use.
   In general this is just CLASS; but on some machines
   in some cases it is preferable to use a more restrictive class.  */

#define PREFERRED_RELOAD_CLASS(X, CLASS) \
  ((CLASS) == NO_REGS && TARGET_SHMEDIA \
   && (GET_CODE (X) == CONST_DOUBLE \
       || GET_CODE (X) == SYMBOL_REF \
       || PIC_DIRECT_ADDR_P (X)) \
   ? GENERAL_REGS \
   : (CLASS)) \

#define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
  ((((REGCLASS_HAS_FP_REG (CLASS) 					\
      && (GET_CODE (X) == REG						\
      && (GENERAL_OR_AP_REGISTER_P (REGNO (X))				\
	  || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode		\
	      && TARGET_FMOVD))))					\
     || (REGCLASS_HAS_GENERAL_REG (CLASS) 				\
	 && GET_CODE (X) == REG						\
	 && FP_REGISTER_P (REGNO (X))))					\
    && ! TARGET_SHMEDIA							\
    && ((MODE) == SFmode || (MODE) == SImode))				\
   ? FPUL_REGS								\
   : (((CLASS) == FPUL_REGS						\
       || (REGCLASS_HAS_FP_REG (CLASS)					\
	   && ! TARGET_SHMEDIA && MODE == SImode))			\
      && (GET_CODE (X) == MEM						\
	  || (GET_CODE (X) == REG					\
	      && (REGNO (X) >= FIRST_PSEUDO_REGISTER			\
		  || REGNO (X) == T_REG					\
		  || system_reg_operand (X, VOIDmode)))))		\
   ? GENERAL_REGS							\
   : (((CLASS) == TARGET_REGS						\
       || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))			\
      && !EXTRA_CONSTRAINT_Csy (X)					\
      && (GET_CODE (X) != REG || ! GENERAL_REGISTER_P (REGNO (X))))	\
   ? GENERAL_REGS							\
   : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS)			\
      && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X))	\
      && (CLASS) != REGNO_REG_CLASS (REGNO (X)))			\
   ? GENERAL_REGS							\
   : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG			\
      && TARGET_REGISTER_P (REGNO (X)))					\
   ? GENERAL_REGS : (ELSE))

#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)

#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X)  \
  ((REGCLASS_HAS_FP_REG (CLASS) 					\
    && ! TARGET_SHMEDIA							\
    && immediate_operand ((X), (MODE))					\
    && ! ((fp_zero_operand (X) || fp_one_operand (X))			\
	  && (MODE) == SFmode && fldi_ok ()))				\
   ? R0_REGS								\
   : ((CLASS) == FPUL_REGS						\
      && ((GET_CODE (X) == REG						\
	   && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG		\
	       || REGNO (X) == T_REG))					\
	  || GET_CODE (X) == PLUS))					\
   ? GENERAL_REGS							\
   : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE))		\
   ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (X))	\
      ? GENERAL_REGS							\
      : R0_REGS)							\
   : ((CLASS) == FPSCR_REGS						\
      && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER)	\
	  || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
   ? GENERAL_REGS							\
   : (REGCLASS_HAS_FP_REG (CLASS) 					\
      && TARGET_SHMEDIA							\
      && immediate_operand ((X), (MODE))				\
      && (X) != CONST0_RTX (GET_MODE (X))				\
      && GET_MODE (X) != V4SFmode)					\
   ? GENERAL_REGS							\
   : (((MODE) == QImode || (MODE) == HImode)				\
      && TARGET_SHMEDIA && inqhi_operand ((X), (MODE)))			\
   ? GENERAL_REGS							\
   : (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS				\
      && (GET_CODE (X) == LABEL_REF || PIC_DIRECT_ADDR_P (X)))		\
   ? TARGET_REGS							\
   : SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))

/* Return the maximum number of consecutive registers
   needed to represent mode MODE in a register of class CLASS.

   If TARGET_SHMEDIA, we need two FP registers per word.
   Otherwise we will need at most one register per word.  */
#define CLASS_MAX_NREGS(CLASS, MODE) \
    (TARGET_SHMEDIA \
     && TEST_HARD_REG_BIT