sh.h

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#endif

#if TARGET_ENDIAN_DEFAULT
#define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
#else
#define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
#endif

#define CPP_SPEC " %(subtarget_cpp_spec) "

#ifndef SUBTARGET_CPP_SPEC
#define SUBTARGET_CPP_SPEC ""
#endif

#ifndef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS
#endif

#define EXTRA_SPECS						\
  { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC },			\
  { "link_emul_prefix", LINK_EMUL_PREFIX },			\
  { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL },		\
  { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX },	\
  { "subtarget_link_spec", SUBTARGET_LINK_SPEC },		\
  { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC },	\
  { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC },	\
  { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC },		\
  { "subtarget_asm_spec", SUBTARGET_ASM_SPEC },			\
  SUBTARGET_EXTRA_SPECS

#if TARGET_CPU_DEFAULT & MASK_HARD_SH4
#define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4}}}}"
#else
#define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4}"
#endif

#define SH_ASM_SPEC \
 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
%(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
%{m2a:--isa=sh2a} \
%{m2a-single:--isa=sh2a} \
%{m2a-single-only:--isa=sh2a} \
%{m2a-nofpu:--isa=sh2a-nofpu} \
%{m5-compact*:--isa=SHcompact} \
%{m5-32media*:--isa=SHmedia --abi=32} \
%{m5-64media*:--isa=SHmedia --abi=64} \
%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"

#define ASM_SPEC SH_ASM_SPEC

#ifndef SUBTARGET_ASM_ENDIAN_SPEC
#if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
#define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
#else
#define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
#endif
#endif

#if STRICT_NOFPU == 1
/* Strict nofpu means that the compiler should tell the assembler
   to reject FPU instructions. E.g. from ASM inserts.  */
#if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
#define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
#else
/* If there were an -isa option for sh5-nofpu then it would also go here. */
#define SUBTARGET_ASM_ISA_SPEC \
 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
#endif
#else /* ! STRICT_NOFPU */
#define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
#endif

#ifndef SUBTARGET_ASM_SPEC
#define SUBTARGET_ASM_SPEC ""
#endif

#if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
#define LINK_EMUL_PREFIX "sh%{!mb:l}"
#else
#define LINK_EMUL_PREFIX "sh%{ml:l}"
#endif

#if TARGET_CPU_DEFAULT & MASK_SH5
#if TARGET_CPU_DEFAULT & MASK_SH_E
#define LINK_DEFAULT_CPU_EMUL "32"
#if TARGET_CPU_DEFAULT & MASK_SH1
#define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
#else
#define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
#endif /* MASK_SH1 */
#else /* !MASK_SH_E */
#define LINK_DEFAULT_CPU_EMUL "64"
#define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
#endif /* MASK_SH_E */
#define ASM_ISA_DEFAULT_SPEC \
" %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
#else /* !MASK_SH5 */
#define LINK_DEFAULT_CPU_EMUL ""
#define ASM_ISA_DEFAULT_SPEC ""
#endif /* MASK_SH5 */

#define SUBTARGET_LINK_EMUL_SUFFIX ""
#define SUBTARGET_LINK_SPEC ""

/* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
   so that we can undo the damage without code replication.  */
#define LINK_SPEC SH_LINK_SPEC

#define SH_LINK_SPEC "\
-m %(link_emul_prefix)\
%{m5-compact*|m5-32media*:32}\
%{m5-64media*:64}\
%{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
%(subtarget_link_emul_suffix) \
%{mrelax:-relax} %(subtarget_link_spec)"

#ifndef SH_DIV_STR_FOR_SIZE
#define SH_DIV_STR_FOR_SIZE "call"
#endif

#define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
#define OPTIMIZATION_OPTIONS(LEVEL,SIZE)				\
do {									\
  if (LEVEL)								\
    {									\
      flag_omit_frame_pointer = -1;					\
      if (! SIZE)							\
	sh_div_str = "inv:minlat";					\
    }									\
  if (SIZE)								\
    {									\
      target_flags |= MASK_SMALLCODE;					\
      sh_div_str = SH_DIV_STR_FOR_SIZE ;				\
    }									\
  /* We can't meaningfully test TARGET_SHMEDIA here, because -m options	\
     haven't been parsed yet, hence we';d read only the default.	\
     sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so	\
     it's OK to always set flag_branch_target_load_optimize.  */	\
  if (LEVEL > 1)							\
    {									\
      flag_branch_target_load_optimize = 1;				\
      if (! (SIZE))							\
	target_flags |= MASK_SAVE_ALL_TARGET_REGS;			\
    }									\
  /* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE	\
     here, so leave it to OVERRIDE_OPTIONS to set			\
    flag_finite_math_only.  We set it to 2 here so we know if the user	\
    explicitly requested this to be on or off.  */			\
  flag_finite_math_only = 2;						\
  /* If flag_schedule_insns is 1, we set it to 2 here so we know if	\
     the user explicitly requested this to be on or off.  */		\
  if (flag_schedule_insns > 0)						\
    flag_schedule_insns = 2;						\
} while (0)

#define ASSEMBLER_DIALECT assembler_dialect

extern int assembler_dialect;

enum sh_divide_strategy_e {
  SH_DIV_CALL,
  SH_DIV_CALL2,
  SH_DIV_FP,
  SH_DIV_INV,
  SH_DIV_INV_MINLAT,
  SH_DIV_INV20U,
  SH_DIV_INV20L,
  SH_DIV_INV_CALL,
  SH_DIV_INV_CALL2,
  SH_DIV_INV_FP
};

extern enum sh_divide_strategy_e sh_div_strategy;

#ifndef SH_DIV_STRATEGY_DEFAULT
#define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
#endif

#define OVERRIDE_OPTIONS 						\
do {									\
  int regno;								\
									\
  if (flag_finite_math_only == 2)					\
    flag_finite_math_only						\
      = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE;		\
  if (TARGET_SH2E && !flag_finite_math_only)				\
    target_flags |= MASK_IEEE;						\
  sh_cpu = CPU_SH1;							\
  assembler_dialect = 0;						\
  if (TARGET_SH2)							\
    sh_cpu = CPU_SH2;							\
  if (TARGET_SH2E)							\
    sh_cpu = CPU_SH2E;							\
  if (TARGET_SH2A)							\
    {									\
      sh_cpu = CPU_SH2A;						\
      if (TARGET_SH2A_DOUBLE)						\
        target_flags |= MASK_FMOVD;					\
    }									\
  if (TARGET_SH3)							\
    sh_cpu = CPU_SH3;							\
  if (TARGET_SH3E)							\
    sh_cpu = CPU_SH3E;							\
  if (TARGET_SH4)							\
    {									\
      assembler_dialect = 1;						\
      sh_cpu = CPU_SH4;							\
    }									\
  if (TARGET_SH4A_ARCH)							\
    {									\
      assembler_dialect = 1;						\
      sh_cpu = CPU_SH4A;						\
    }									\
  if (TARGET_SH5)							\
    {									\
      sh_cpu = CPU_SH5;							\
      target_flags |= MASK_ALIGN_DOUBLE;				\
      if (TARGET_SHMEDIA_FPU)						\
	target_flags |= MASK_FMOVD;					\
      if (TARGET_SHMEDIA)						\
	{								\
	  /* There are no delay slots on SHmedia.  */			\
	  flag_delayed_branch = 0;					\
	  /* Relaxation isn't yet supported for SHmedia */		\
	  target_flags &= ~MASK_RELAX;					\
	  /* After reload, if conversion does little good but can cause \
	     ICEs:							\
	     - find_if_block doesn't do anything for SH because we don't\
	       have conditional execution patterns.  (We use conditional\
	       move patterns, which are handled differently, and only	\
	       before reload).						\
	     - find_cond_trap doesn't do anything for the SH because we \	
	       don't have conditional traps.				\
	     - find_if_case_1 uses redirect_edge_and_branch_force in	\
	       the only path that does an optimization, and this causes	\
	       an ICE when branch targets are in registers.		\
	     - find_if_case_2 doesn't do anything for the SHmedia after	\
	       reload except when it can redirect a tablejump - and	\
	       that's rather rare.  */					\
	  flag_if_conversion2 = 0;					\
	  if (! strcmp (sh_div_str, "call"))				\
	    sh_div_strategy = SH_DIV_CALL;				\
	  else if (! strcmp (sh_div_str, "call2"))			\
	    sh_div_strategy = SH_DIV_CALL2;				\
	  if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY)		\
	    sh_div_strategy = SH_DIV_FP;				\
	  else if (! strcmp (sh_div_str, "inv"))			\
	    sh_div_strategy = SH_DIV_INV;				\
	  else if (! strcmp (sh_div_str, "inv:minlat"))			\
	    sh_div_strategy = SH_DIV_INV_MINLAT;			\
	  else if (! strcmp (sh_div_str, "inv20u"))			\
	    sh_div_strategy = SH_DIV_INV20U;				\
	  else if (! strcmp (sh_div_str, "inv20l"))			\
	    sh_div_strategy = SH_DIV_INV20L;				\
	  else if (! strcmp (sh_div_str, "inv:call2"))			\
	    sh_div_strategy = SH_DIV_INV_CALL2;				\
	  else if (! strcmp (sh_div_str, "inv:call"))			\
	    sh_div_strategy = SH_DIV_INV_CALL;				\
	  else if (! strcmp (sh_div_str, "inv:fp"))			\
	    {								\
	      if (TARGET_FPU_ANY)					\
		sh_div_strategy = SH_DIV_INV_FP;			\
	      else							\
		sh_div_strategy = SH_DIV_INV;				\
	    }								\
	}								\
      /* -fprofile-arcs needs a working libgcov .  In unified tree	\
	 configurations with newlib, this requires to configure with	\
	 --with-newlib --with-headers.  But there is no way to check	\
	 here we have a working libgcov, so just assume that we have.  */\
      if (profile_flag)							\
	warning (0, "profiling is still experimental for this target");\
    }									\
  else									\
    {									\
       /* Only the sh64-elf assembler fully supports .quad properly.  */\
       targetm.asm_out.aligned_op.di = NULL;				\
       targetm.asm_out.unaligned_op.di = NULL;				\
    }									\
  if (sh_divsi3_libfunc[0])						\
    ; /* User supplied - leave it alone.  */				\
  else if (TARGET_HARD_SH4 && TARGET_SH2E)				\
    sh_divsi3_libfunc = "__sdivsi3_i4";					\
  else if (TARGET_SH5)							\
    {									\
      if (TARGET_FPU_ANY && TARGET_SH1)					\
	sh_divsi3_libfunc = "__sdivsi3_i4";				\
      else								\
	sh_divsi3_libfunc = "__sdivsi3_1";				\
    }									\
  else									\
    sh_divsi3_libfunc = "__sdivsi3";					\
  if (TARGET_FMOVD)							\
    reg_class_from_letter['e' - 'a'] = NO_REGS;				\
									\
  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)		\
    if (! VALID_REGISTER_P (regno))					\
      sh_register_names[regno][0] = '\0';				\
									\
  for (regno = 0; regno < ADDREGNAMES_SIZE; regno++)			\
    if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno)))			\
      sh_additional_register_names[regno][0] = '\0';			\
									\
  if (flag_omit_frame_pointer < 0)					\
   {									\
     /* The debugging information is sufficient,			\
        but gdb doesn't implement this yet */				\
     if (0)								\
      flag_omit_frame_pointer						\
        = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG);			\
     else								\
      flag_omit_frame_pointer = 0;					\
   }									\
									\
  if ((flag_pic && ! TARGET_PREFERGOT)					\
      || (TARGET_SHMEDIA && !TARGET_PT_FIXED))				\
    flag_no_function_cse = 1;						\
									\
  if (SMALL_REGISTER_CLASSES)						\
    {									\
      /* Never run scheduling before reload, since that can		\
	 break global alloc, and generates slower code anyway due	\
	 to the pressure on R0.  */					\
      /* Enable sched1 for SH4; ready queue will be reordered by	\
	 the target hooks when pressure is high. We can not do this for \
	 SH3 and lower as they give spill failures for R0.  */		\
      if (!TARGET_HARD_SH4) 						\
        flag_schedule_insns = 0;		 			\
      /* ??? Current exception handling places basic block boundaries	\
	 after call_insns.  It causes the high pressure on R0 and gives	\
	 spill failures for R0 in reload.  See PR 22553 and the thread	\
	 on gcc-patches							\
         <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>.  */	\
      else if (flag_exceptions)						\
	{								\
	  if (flag_schedule_insns == 1)		 			\
	    warning (0, "ignoring -fschedule-insns because of exception handling bug");	\
	  flag_schedule_insns = 0;		 			\
	}								\