sh.h

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/* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
   Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
   2003, 2004, 2005, 2006 Free Software Foundation, Inc.
   Contributed by Steve Chamberlain ([e-mail]).
   Improved by Jim Wilson ([e-mail]).

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING.  If not, write to
the Free Software Foundation, 51 Franklin Street, Fifth Floor,
Boston, MA 02110-1301, USA.  */

#ifndef GCC_SH_H
#define GCC_SH_H

#define TARGET_VERSION \
  fputs (" (Hitachi SH)", stderr);

/* Unfortunately, insn-attrtab.c doesn't include insn-codes.h.  We can't
   include it here, because bconfig.h is also included by gencodes.c .  */
/* ??? No longer true.  */
extern int code_for_indirect_jump_scratch;

#define TARGET_CPU_CPP_BUILTINS() \
do { \
  builtin_define ("__sh__"); \
  builtin_assert ("cpu=sh"); \
  builtin_assert ("machine=sh"); \
  switch ((int) sh_cpu) \
    { \
    case PROCESSOR_SH1: \
      builtin_define ("__sh1__"); \
      break; \
    case PROCESSOR_SH2: \
      builtin_define ("__sh2__"); \
      break; \
    case PROCESSOR_SH2E: \
      builtin_define ("__SH2E__"); \
      break; \
    case PROCESSOR_SH2A: \
      builtin_define ("__SH2A__"); \
      builtin_define (TARGET_SH2A_DOUBLE \
		      ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
		      : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
		      : "__SH2A_NOFPU__"); \
      break; \
    case PROCESSOR_SH3: \
      builtin_define ("__sh3__"); \
      builtin_define ("__SH3__"); \
      if (TARGET_HARD_SH4) \
	builtin_define ("__SH4_NOFPU__"); \
      break; \
    case PROCESSOR_SH3E: \
      builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
      break; \
    case PROCESSOR_SH4: \
      builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
      break; \
    case PROCESSOR_SH4A: \
      builtin_define ("__SH4A__"); \
      builtin_define (TARGET_SH4 \
		      ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
		      : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
		      : "__SH4_NOFPU__"); \
      break; \
    case PROCESSOR_SH5: \
      { \
	builtin_define_with_value ("__SH5__", \
				   TARGET_SHMEDIA64 ? "64" : "32", 0); \
	builtin_define_with_value ("__SHMEDIA__", \
				   TARGET_SHMEDIA ? "1" : "0", 0); \
	if (! TARGET_FPU_DOUBLE) \
	  builtin_define ("__SH4_NOFPU__"); \
      } \
    } \
  if (TARGET_FPU_ANY) \
    builtin_define ("__SH_FPU_ANY__"); \
  if (TARGET_FPU_DOUBLE) \
    builtin_define ("__SH_FPU_DOUBLE__"); \
  if (TARGET_HITACHI) \
    builtin_define ("__HITACHI__"); \
  builtin_define (TARGET_LITTLE_ENDIAN \
		  ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
  if (flag_pic) \
    { \
      builtin_define ("__pic__"); \
      builtin_define ("__PIC__"); \
    } \
} while (0)

/* We can not debug without a frame pointer.  */
/* #define CAN_DEBUG_WITHOUT_FP */

#define CONDITIONAL_REGISTER_USAGE do					\
{									\
  int regno;								\
  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++)		\
    if (! VALID_REGISTER_P (regno))					\
      fixed_regs[regno] = call_used_regs[regno] = 1;			\
  /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs.  */ \
  if (TARGET_SH5)							\
    {									\
      call_used_regs[FIRST_GENERAL_REG + 8]				\
	= call_used_regs[FIRST_GENERAL_REG + 9] = 1;			\
      call_really_used_regs[FIRST_GENERAL_REG + 8]			\
	= call_really_used_regs[FIRST_GENERAL_REG + 9] = 1;		\
    }									\
  if (TARGET_SHMEDIA)							\
    {									\
      regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS;		\
      CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]);		\
      regno_reg_class[FIRST_FP_REG] = FP_REGS;				\
    }									\
  if (flag_pic)								\
    {									\
      fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;				\
      call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;			\
    }									\
  /* Renesas saves and restores mac registers on call.  */		\
  if (TARGET_HITACHI && ! TARGET_NOMACSAVE)				\
    {									\
      call_really_used_regs[MACH_REG] = 0;				\
      call_really_used_regs[MACL_REG] = 0;				\
    }									\
  for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0);		\
       regno <= LAST_FP_REG; regno += 2)				\
    SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno);		\
  if (TARGET_SHMEDIA)							\
    {									\
      for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
	if (! fixed_regs[regno] && call_really_used_regs[regno])	\
	  SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno);	\
    }									\
  else									\
    for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++)	\
      if (! fixed_regs[regno] && call_really_used_regs[regno])		\
	SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno);	\
} while (0)

/* Nonzero if this is an ELF target - compile time only */
#define TARGET_ELF 0

/* Nonzero if we should generate code using type 2E insns.  */
#define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)

/* Nonzero if we should generate code using type 2A insns.  */
#define TARGET_SH2A TARGET_HARD_SH2A
/* Nonzero if we should generate code using type 2A SF insns.  */
#define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
/* Nonzero if we should generate code using type 2A DF insns.  */
#define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)

/* Nonzero if we should generate code using type 3E insns.  */
#define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)

/* Nonzero if the cache line size is 32.  */
#define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)

/* Nonzero if we schedule for a superscalar implementation.  */
#define TARGET_SUPERSCALAR TARGET_HARD_SH4

/* Nonzero if the target has separate instruction and data caches.  */
#define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)

/* Nonzero if a double-precision FPU is available.  */
#define TARGET_FPU_DOUBLE \
  ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)

/* Nonzero if an FPU is available.  */
#define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)

/* Nonzero if we should generate code using type 4 insns.  */
#undef TARGET_SH4
#define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)

/* Nonzero if we're generating code for the common subset of
   instructions present on both SH4a and SH4al-dsp.  */
#define TARGET_SH4A_ARCH TARGET_SH4A

/* Nonzero if we're generating code for SH4a, unless the use of the
   FPU is disabled (which makes it compatible with SH4al-dsp).  */
#define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)

/* Nonzero if we should generate code using the SHcompact instruction
   set and 32-bit ABI.  */
#define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)

/* Nonzero if we should generate code using the SHmedia instruction
   set and ABI.  */
#define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)

/* Nonzero if we should generate code using the SHmedia ISA and 32-bit
   ABI.  */
#define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)

/* Nonzero if we should generate code using the SHmedia ISA and 64-bit
   ABI.  */
#define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)

/* Nonzero if we should generate code using SHmedia FPU instructions.  */
#define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)

/* This is not used by the SH2E calling convention  */
#define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
  (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
   && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))

#ifndef TARGET_CPU_DEFAULT
#define TARGET_CPU_DEFAULT SELECT_SH1
#define SUPPORT_SH1 1
#define SUPPORT_SH2E 1
#define SUPPORT_SH4 1
#define SUPPORT_SH4_SINGLE 1
#define SUPPORT_SH2A 1
#define SUPPORT_SH2A_SINGLE 1
#endif

#define TARGET_DIVIDE_INV \
  (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
   || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
   || sh_div_strategy == SH_DIV_INV_CALL \
   || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
#define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
#define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
#define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
#define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
#define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
#define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
#define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
#define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)

#define SELECT_SH1               (MASK_SH1)
#define SELECT_SH2               (MASK_SH2 | SELECT_SH1)
#define SELECT_SH2E              (MASK_SH_E | MASK_SH2 | MASK_SH1 \
				  | MASK_FPU_SINGLE)
#define SELECT_SH2A              (MASK_SH_E | MASK_HARD_SH2A \
				  | MASK_HARD_SH2A_DOUBLE \
				  | MASK_SH2 | MASK_SH1)
#define SELECT_SH2A_NOFPU        (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
#define SELECT_SH2A_SINGLE_ONLY  (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
				  | MASK_SH1 | MASK_FPU_SINGLE)
#define SELECT_SH2A_SINGLE       (MASK_SH_E | MASK_HARD_SH2A \
				  | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
				  | MASK_SH2 | MASK_SH1)
#define SELECT_SH3               (MASK_SH3 | SELECT_SH2)
#define SELECT_SH3E              (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
#define SELECT_SH4_NOFPU         (MASK_HARD_SH4 | SELECT_SH3)
#define SELECT_SH4_SINGLE_ONLY   (MASK_HARD_SH4 | SELECT_SH3E)
#define SELECT_SH4               (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
				  | SELECT_SH3)
#define SELECT_SH4_SINGLE        (MASK_FPU_SINGLE | SELECT_SH4)
#define SELECT_SH4A_NOFPU        (MASK_SH4A | SELECT_SH4_NOFPU)
#define SELECT_SH4A_SINGLE_ONLY  (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
#define SELECT_SH4A              (MASK_SH4A | SELECT_SH4)
#define SELECT_SH4A_SINGLE       (MASK_SH4A | SELECT_SH4_SINGLE)
#define SELECT_SH5_64MEDIA       (MASK_SH5 | MASK_SH4)
#define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
#define SELECT_SH5_32MEDIA       (MASK_SH5 | MASK_SH4 | MASK_SH_E)
#define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
#define SELECT_SH5_COMPACT       (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
#define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)

#if SUPPORT_SH1
#define SUPPORT_SH2 1
#endif
#if SUPPORT_SH2
#define SUPPORT_SH3 1
#endif
#if SUPPORT_SH3
#define SUPPORT_SH4_NOFPU 1
#endif
#if SUPPORT_SH4_NOFPU
#define SUPPORT_SH4A_NOFPU 1
#define SUPPORT_SH4AL 1
#define SUPPORT_SH2A_NOFPU 1
#endif

#if SUPPORT_SH2E
#define SUPPORT_SH3E 1
#endif
#if SUPPORT_SH3E
#define SUPPORT_SH4_SINGLE_ONLY 1
#define SUPPORT_SH4A_SINGLE_ONLY 1
#define SUPPORT_SH2A_SINGLE_ONLY 1
#endif

#if SUPPORT_SH4
#define SUPPORT_SH4A 1
#endif

#if SUPPORT_SH4_SINGLE
#define SUPPORT_SH4A_SINGLE 1
#endif

#if SUPPORT_SH5_COMPAT
#define SUPPORT_SH5_32MEDIA 1
#endif

#if SUPPORT_SH5_COMPACT_NOFPU
#define SUPPORT_SH5_32MEDIA_NOFPU 1
#endif

#define SUPPORT_ANY_SH5_32MEDIA \
  (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
#define SUPPORT_ANY_SH5_64MEDIA \
  (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
#define SUPPORT_ANY_SH5 \
  (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)

/* Reset all target-selection flags.  */
#define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
		   | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
		   | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)

/* This defaults us to big-endian.  */
#ifndef TARGET_ENDIAN_DEFAULT
#define TARGET_ENDIAN_DEFAULT 0
#endif

#ifndef TARGET_OPT_DEFAULT
#define TARGET_OPT_DEFAULT  MASK_ADJUST_UNROLL
#endif

#define TARGET_DEFAULT \
  (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)

#ifndef SH_MULTILIB_CPU_DEFAULT
#define SH_MULTILIB_CPU_DEFAULT "m1"