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  [(set_attr "type" "cmp_media")])

(define_insn "cmpgtusi_media"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(gtu:DI (match_operand:SI 1 "cmp_operand" "Nr")
		(match_operand:SI 2 "cmp_operand" "rN")))]
  "TARGET_SHMEDIA"
  "cmpgtu	%N1, %N2, %0"
  [(set_attr "type" "cmp_media")])

(define_insn "cmpgtudi_media"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(gtu:DI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
		(match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
  "TARGET_SHMEDIA"
  "cmpgtu	%N1, %N2, %0"
  [(set_attr "type" "cmp_media")])

(define_insn "cmpsieqsi_media"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(eq:SI (match_operand:SI 1 "logical_operand" "%r")
	       (match_operand:SI 2 "cmp_operand" "Nr")))]
  "TARGET_SHMEDIA"
  "cmpeq	%1, %N2, %0"
  [(set_attr "type" "cmp_media")])

(define_insn "cmpsieqdi_media"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(eq:SI (match_operand:DI 1 "register_operand" "%r")
	       (match_operand:DI 2 "cmp_operand" "Nr")))]
  "TARGET_SHMEDIA"
  "cmpeq	%1, %N2, %0"
  [(set_attr "type" "cmp_media")])

(define_insn "cmpsigtsi_media"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(gt:SI (match_operand:SI 1 "cmp_operand" "Nr")
	       (match_operand:SI 2 "cmp_operand" "rN")))]
  "TARGET_SHMEDIA"
  "cmpgt	%N1, %N2, %0"
  [(set_attr "type" "cmp_media")])

(define_insn "cmpsigtdi_media"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(gt:SI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
	       (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
  "TARGET_SHMEDIA"
  "cmpgt	%N1, %N2, %0"
  [(set_attr "type" "cmp_media")])

(define_insn "cmpsigtusi_media"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(gtu:SI (match_operand:SI 1 "cmp_operand" "Nr")
		(match_operand:SI 2 "cmp_operand" "rN")))]
  "TARGET_SHMEDIA"
  "cmpgtu	%N1, %N2, %0"
  [(set_attr "type" "cmp_media")])

(define_insn "cmpsigtudi_media"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(gtu:SI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
		(match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
  "TARGET_SHMEDIA"
  "cmpgtu	%N1, %N2, %0"
  [(set_attr "type" "cmp_media")])

; These two patterns are for combine.
(define_insn "*cmpne0si_media"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(ne:DI (match_operand:SI 1 "arith_reg_operand" "r") (const_int 0)))]
  "TARGET_SHMEDIA"
  "cmpgtu	%1,r63,%0"
  [(set_attr "type" "cmp_media")])

(define_insn "*cmpne0sisi_media"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ne:SI (match_operand:SI 1 "arith_reg_operand" "r") (const_int 0)))]
  "TARGET_SHMEDIA"
  "cmpgtu	%1,r63,%0"
  [(set_attr "type" "cmp_media")])

;; We save the compare operands in the cmpxx patterns and use them when
;; we generate the branch.

(define_expand "cmpdi"
  [(set (reg:SI T_REG)
	(compare (match_operand:DI 0 "arith_operand" "")
		 (match_operand:DI 1 "arith_operand" "")))]
  "TARGET_SH2 || TARGET_SHMEDIA"
  "
{
  sh_compare_op0 = operands[0];
  sh_compare_op1 = operands[1];
  DONE;
}")
;; -------------------------------------------------------------------------
;; Conditional move instructions
;; -------------------------------------------------------------------------

;; The insn names may seem reversed, but note that cmveq performs the move
;; if op1 == 0, and cmvne does it if op1 != 0.

(define_insn "movdicc_false"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
	(if_then_else:DI (eq (match_operand:DI 1 "arith_reg_operand" "r")
			     (const_int 0))
	 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
	 (match_operand:DI 3 "arith_reg_operand" "0")))]
  "TARGET_SHMEDIA"
  "cmveq	%1, %N2, %0"
  [(set_attr "type" "arith_media")])

(define_insn "movdicc_true"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
	(if_then_else:DI (ne (match_operand:DI 1 "arith_reg_operand" "r")
			     (const_int 0))
	 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
	 (match_operand:DI 3 "arith_reg_operand" "0")))]
  "TARGET_SHMEDIA"
  "cmvne	%1, %N2, %0"
  [(set_attr "type" "arith_media")])

(define_peephole2
  [(set (match_operand:DI 0 "arith_reg_dest" "")
	(if_then_else:DI (match_operator 3 "equality_comparison_operator"
			   [(match_operand:DI 1 "arith_reg_operand" "")
			    (const_int 0)])
	 (match_operand:DI 2 "arith_reg_dest" "")
	 (match_dup 0)))
   (set (match_dup 2) (match_dup 0))]
  "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
  [(set (match_dup 2)
	(if_then_else:DI (match_dup 3) (match_dup 0) (match_dup 2)))]
  "
{
  operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[3])),
				VOIDmode, operands[1], CONST0_RTX (DImode));
}")

(define_peephole2
  [(set (match_operand:DI 0 "general_movdst_operand" "")
	(match_operand:DI 1 "arith_reg_or_0_operand" ""))
   (set (match_operand:DI 2 "arith_reg_dest" "")
	(if_then_else:DI (match_operator 4 "equality_comparison_operator"
			   [(match_operand:DI 3 "arith_reg_operand" "")
			    (const_int 0)])
	 (match_dup 0)
	 (match_dup 2)))]
  "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
  [(set (match_dup 2)
	(if_then_else:DI (match_dup 4) (match_dup 1) (match_dup 2)))]
  "")

(define_expand "movdicc"
  [(set (match_operand:DI 0 "register_operand" "")
	(if_then_else:DI (match_operand 1 "comparison_operator" "")
			 (match_operand:DI 2 "register_operand" "")
			 (match_operand:DI 3 "register_operand" "")))]
  "TARGET_SHMEDIA"
  "
{
  if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
      && GET_MODE (sh_compare_op0) == DImode
      && sh_compare_op1 == const0_rtx)
    operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
				  sh_compare_op0, sh_compare_op1);
  else
    {
      rtx tmp;

      if (no_new_pseudos)
	FAIL;

      tmp = gen_reg_rtx (DImode);

      switch (GET_CODE (operands[1]))
	{
	case EQ:
	  emit_insn (gen_seq (tmp));
	  operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
	  break;

	case NE:
	  emit_insn (gen_seq (tmp));
	  operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
	  break;

	case GT:
	  emit_insn (gen_sgt (tmp));
	  operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
	  break;

	case LT:
	  emit_insn (gen_slt (tmp));
	  operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
	  break;

	case GE:
	  emit_insn (gen_slt (tmp));
	  operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
	  break;

	case LE:
	  emit_insn (gen_sgt (tmp));
	  operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
	  break;

	case GTU:
	  emit_insn (gen_sgtu (tmp));
	  operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
	  break;

	case LTU:
	  emit_insn (gen_sltu (tmp));
	  operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
	  break;

	case GEU:
	  emit_insn (gen_sltu (tmp));
	  operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
	  break;

	case LEU:
	  emit_insn (gen_sgtu (tmp));
	  operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
	  break;

	case UNORDERED:
	  emit_insn (gen_sunordered (tmp));
	  operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
	  break;

	case ORDERED:
	  emit_insn (gen_sunordered (tmp));
	  operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
	  break;

	case UNEQ:
	case UNGE:
	case UNGT:
	case UNLE:
	case UNLT:
	case LTGT:
	  FAIL;

	default:
	  gcc_unreachable ();
	}
    }
}")

;; Add SImode variants for cmveq / cmvne to compensate for not promoting
;; SImode to DImode.
(define_insn "movsicc_false"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
	(if_then_else:SI (eq (match_operand:SI 1 "arith_reg_operand" "r")
			  (const_int 0))
	 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
	 (match_operand:SI 3 "arith_reg_operand" "0")))]
  "TARGET_SHMEDIA"
  "cmveq	%1, %N2, %0"
  [(set_attr "type" "arith_media")])

(define_insn "movsicc_true"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
	(if_then_else:SI (ne (match_operand:SI 1 "arith_reg_operand" "r")
			  (const_int 0))
	 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
	 (match_operand:SI 3 "arith_reg_operand" "0")))]
  "TARGET_SHMEDIA"
  "cmvne	%1, %N2, %0"
  [(set_attr "type" "arith_media")])

(define_peephole2
  [(set (match_operand:SI 0 "arith_reg_dest" "")
	(if_then_else:SI (match_operator 3 "equality_comparison_operator"
			   [(match_operand:SI 1 "arith_reg_operand" "")
			    (const_int 0)])
	 (match_operand:SI 2 "arith_reg_dest" "")
	 (match_dup 0)))
   (set (match_dup 2) (match_dup 0))]
  "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
  [(set (match_dup 2)
	(if_then_else:SI (match_dup 3) (match_dup 0) (match_dup 2)))]
  "
{
  operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[3])),
				VOIDmode, operands[1], CONST0_RTX (SImode));
}")

(define_peephole2
  [(set (match_operand:SI 0 "general_movdst_operand" "")
	(match_operand:SI 1 "arith_reg_or_0_operand" ""))
   (set (match_operand:SI 2 "arith_reg_dest" "")
	(if_then_else:SI (match_operator 4 "equality_comparison_operator"
			   [(match_operand:SI 3 "arith_reg_operand" "")
			    (const_int 0)])
	 (match_dup 0)
	 (match_dup 2)))]
  "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])
   && (GET_CODE (operands[1]) != REG || GENERAL_REGISTER_P (REGNO (operands[1])))"
  [(set (match_dup 2)
	(if_then_else:SI (match_dup 4) (match_dup 1) (match_dup 2)))]
  "
{
  replace_rtx (operands[4], operands[0], operands[1]);
}")

(define_peephole2
  [(set (match_operand 0 "any_register_operand" "")
	(match_operand 1 "any_register_operand" ""))
   (set (match_operand 2 "any_register_operand" "") (match_operand 3 "" ""))
   (set (match_operand 4 "" "") (match_operand 5 "" ""))]
  "(HARD_REGNO_NREGS (REGNO (operands[0]), GET_MODE (operands[2]))
    <= HARD_REGNO_NREGS (REGNO (operands[0]), GET_MODE (operands[0])))
   && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[2])
   && ! reg_overlap_mentioned_p (operands[0], operands[3])
   && ! reg_overlap_mentioned_p (operands[2], operands[0])
   && ! reg_overlap_mentioned_p (operands[0], operands[1])
   && (REGNO_REG_CLASS (REGNO (operands[0]))
       == REGNO_REG_CLASS (REGNO (operands[2])))
   && (REGNO_REG_CLASS (REGNO (operands[1]))
       == REGNO_REG_CLASS (REGNO (operands[0])))"
  [(set (match_dup 0) (match_dup 3))
   (set (match_dup 4) (match_dup 5))]
  "
{
  rtx set1, set2;
  rtx replacements[4];

  /* We want to replace occurrences of operands[0] with operands[1] and
     operands[2] with operands[0] in operands[4]/operands[5].
     Doing just two replace_rtx calls naively would result in the second
     replacement undoing all that the first did if operands[1] and operands[2]
     are identical, so we must do this simultaneously.  */
  replacements[0] = operands[0];
  replacements[1] = operands[1];
  replacements[2] = operands[2];
  replacements[3] = operands[0];
  if (!replace_n_hard_rtx (operands[5], replacements, 2, 0)
      || !replace_n_hard_rtx (operands[4], replacements, 2, 0)
      || !replace_n_hard_rtx (operands[2], replacements, 2, 0))
    FAIL;

  operands[5] = replace_n_hard_rtx (operands[5], replacements, 2, 1);
  replace_n_hard_rtx (operands[4], replacements, 2, 1);
  operands[2] = replace_n_hard_rtx (operands[2], replacements, 2, 1);
  /* The operands array is aliased to recog_data.operand, which gets
     clobbered by extract_insn, so finish with it now.  */
  set1 = gen_rtx_SET (VOIDmode, operands[2], operands[3]);
  set2 = gen_rtx_SET (VOIDmode, operands[4], operands[5]);
  /* ??? The last insn might be a jump insn, but the generic peephole2 code
     always uses emit_insn.  */
  /* Check that we don't violate matching constraints or earlyclobbers.  */
  extract_insn (emit_insn (set1));
  if (! constrain_operands (1))
    goto failure;
  extract_insn (emit (set2));
  if (! constrain_operands (1))
    {
      rtx tmp;
    failure:
      tmp = replacements[0];
      replacements[0] = replacements[1];
      replacements[1] = tmp;
      tmp = replacements[2];
      replacements[2] = replacements[3];
      replacements[3] = tmp;
      replace_n_hard_rtx (SET_DEST (set1), replacements, 2, 1);
      replace_n_hard_rtx (SET_DEST (set2), replacements, 2, 1);
      replace_n_hard_rtx (SET_SRC (set2), replacements, 2, 1);
      FAIL;
    }
  DONE;
}")

;; The register allocator is rather clumsy in handling multi-way conditional
;; moves, so allow the combiner to make them, and we split them up after
;; reload.  */
(define_insn_and_split "*movsicc_umin"
  [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
	(umin:SI (if_then_else:SI
		   (eq (match_operand:SI 1 "arith_reg_operand" "r")
		       (const_int 0))
		   (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
		   (match_operand:SI 3 "register_operand" "0"))
		 (match_operand:SI 4 "arith_reg_or_0_operand" "r")))
   (clobber (match_scratch:SI 5 "=&r"))]
  "TARGET_SHMEDIA && no_new_pseudos"
  "#"