cpu_cm.h

VRTX操作系统

/*************************************************************************

	Copyright (c) 1999 Mentor Graphics Corporation.


IMPORTANT - USE OF THIS SOFTWARE IS SUBJECT TO LICENSE RESTRICTIONS
CAREFULLY READ THE LICENSE AGREEMENT BEFORE USING THE SOFTWARE


*************************************************************************/

#ifndef _CPU_CACHE_MMU_
#define _CPU_CACHE_MMU_

#ifdef __cplusplus
extern "C" {
#endif

#include <ansiprot.h>

/*
 * Cache/MMU abstract data type definitions
 */

typedef unsigned cpu_cm_word;
typedef cpu_cm_word cpu_cm_return_t;
typedef cpu_cm_word cpu_cm_cd_t;
typedef cpu_cm_word cpu_cm_id_t;
typedef cpu_cm_word cpu_cm_addr_t;
typedef cpu_cm_word cpu_cm_attr_t;
typedef cpu_cm_word cpu_cm_cmode_t;
typedef cpu_cm_word cpu_cm_cstat_t;
typedef cpu_cm_word cpu_cm_size_t;
typedef cpu_cm_word cpu_cm_mmu_mode_t;
typedef cpu_cm_word cpu_cm_mmu_prot_t;
typedef cpu_cm_word cpu_cm_mmu_rtype_t;
typedef cpu_cm_word cpu_cm_mconfig_t;
typedef cpu_cm_word cpu_cm_init_type_t;

struct cpu_cm_cinfo_s {
	cpu_cm_cmode_t		cmi_cache_mode;
	cpu_cm_cstat_t		cmi_status;
	};

typedef struct cpu_cm_cinfo_s cpu_cm_cinfo_t;



/*
 * Cache/MMU support function prototypes 
 */

/*
 * Cache functions
 */

extern cpu_cm_return_t 
cpu_cache_attributes(ANSIPROT6(	
	cpu_cm_id_t		id,
	cpu_cm_cd_t		cache_designator,
	cpu_cm_addr_t		address,	
        cpu_cm_size_t           size,
	cpu_cm_cmode_t		*cmode_ptr,
        cpu_cm_size_t           *remaining_ptr));

extern cpu_cm_return_t
cpu_cache_disable_all(ANSIPROT1(cpu_cm_cd_t	cache_designator));

extern cpu_cm_return_t
cpu_cache_enable_all(ANSIPROT1(cpu_cm_cd_t	cache_designator));

extern cpu_cm_return_t
cpu_cache_flush(ANSIPROT4(
	cpu_cm_id_t		id,
	cpu_cm_cd_t		cache_designator,
	cpu_cm_addr_t		address,
	cpu_cm_size_t		size));

extern cpu_cm_return_t
cpu_cache_flush_all(ANSIPROT1(cpu_cm_cd_t	cache_designator));

extern cpu_cm_return_t
cpu_cache_info(ANSIPROT1(cpu_cm_cinfo_t *info_ptr));

extern cpu_cm_return_t
cpu_cache_invalidate(ANSIPROT4(
        cpu_cm_id_t             id,
        cpu_cm_cd_t             cache_designator,
        cpu_cm_addr_t           address,
        cpu_cm_size_t           size));

extern cpu_cm_return_t
cpu_cache_invalidate_all(ANSIPROT1(cpu_cm_cd_t	cache_designator));

/*
 * MMU functions
 */

struct cpu_cm_init_s {
	cpu_cm_addr_t	cm_page_mem_start;
	cpu_cm_addr_t	cm_page_mem_end;
	};

typedef struct cpu_cm_init_s cpu_cm_init_t;

extern cpu_cm_return_t
cpu_cm_init_begin(ANSIPROT1(cpu_cm_init_t *mem_params));

extern cpu_cm_return_t
cpu_cm_init_map(ANSIPROT7(
	cpu_cm_init_type_t	type,
        cpu_cm_addr_t           address,
        cpu_cm_size_t           size,
	cpu_cm_mmu_prot_t	mmu_protection,
	cpu_cm_mmu_mode_t	mmu_mode,
	cpu_cm_cmode_t		i_cache_mode,
	cpu_cm_cmode_t		d_cache_mode));

extern cpu_cm_return_t
cpu_cm_init_terminate(ANSIPROT0);

extern cpu_cm_return_t
cpu_cache_set(ANSIPROT5(
        cpu_cm_id_t             id,
	cpu_cm_cd_t		cache_designator,
        cpu_cm_addr_t           address,
        cpu_cm_size_t           size,
	cpu_cm_cmode_t		cache_mode));

struct cpu_cm_mattr_s {
	cpu_cm_mmu_mode_t	mmu_mode;
	cpu_cm_mmu_prot_t	mmu_protection;
	};
typedef struct cpu_cm_mattr_s cpu_cm_mattr_t;

extern cpu_cm_return_t
cpu_mmu_get_attributes(ANSIPROT6(
        cpu_cm_id_t             id,
	cpu_cm_mmu_rtype_t	reg_type,
        cpu_cm_addr_t           address,
        cpu_cm_size_t           size,
	cpu_cm_mattr_t		*mattr_ptr,
	cpu_cm_size_t		*remaining_ptr));



struct cpu_cm_minfo_s {
	cpu_cm_mconfig_t	mmu_config;
	};
typedef struct cpu_cm_minfo_s cpu_cm_minfo_t;

extern cpu_cm_return_t
cpu_mmu_info(ANSIPROT1(cpu_cm_minfo_t		*minfo_ptr));

extern cpu_cm_return_t
cpu_mmu_set_attributes(ANSIPROT5(
        cpu_cm_id_t             id,
	cpu_cm_mmu_rtype_t	reg_type,
        cpu_cm_addr_t           address,
	cpu_cm_size_t           size,
	cpu_cm_mattr_t		*mattr_ptr));


extern cpu_cm_return_t
cpu_mmu_vtop(ANSIPROT4(
        cpu_cm_id_t             id,
        cpu_cm_addr_t           address,
	cpu_cm_addr_t		*paddress_ptr,
	cpu_cm_size_t		*remaining_ptr));


/*
 * PAGE SIZE
 */

/* 
** Following conditional is temporary until all the rest of the targets
** are changed over to get this value via a function.
*/
#if defined(I960)

extern cpu_cm_size_t 
cpu_cm_page_size(ANSIPROT0);

#define CPU_CM_PAGE_SIZE cpu_cm_page_size()

#else 
#define CPU_CM_PAGE_SIZE 4096
#endif

/*
 * Cache/MMU Function Return Codes
 */
#define	CPU_CM_SUCCESS		0	/* Successfull Completion */
#define	CPU_CM_NO_CACHE		1	/* Cache support not configured */
#define	CPU_CM_NO_MMU		2	/* MMU support not configured */
#define	CPU_CM_IADDR		3	/* Invalid Address */
#define	CPU_CM_IRANGE		4	/* Invalid address range (address + size - 1) */
#define	CPU_CM_ICDES		5	/* Invalid cache desiginator */
#define	CPU_CM_ICMODE		6	/* Invalid cache mode */
#define	CPU_CM_IMMODE		7	/* Invalid MMU access mode */
#define	CPU_CM_IMPROT		8	/* Invalid MMU access mode */
#define	CPU_CM_ITYPE		9	/* Invalid type */
#define	CPU_CM_FAILURE		10	/* Not Successfull (false) */

/*
 * init type parameter
 */
#define	CPU_CM_INIT_MMU		0
#define	CPU_CM_INIT_OTHER	1


/*
 * for the id field used on most cache/MMU functions
 */
#define	CPU_CM_CURRENT_TASK 0

/*
 * Cache status used in cpu_cm_cinfo_s
 */
#define CPU_CACHE_INSTRUCTION_ENABLED	1
#define CPU_CACHE_DATA_ENABLED		2
/*
 * cache designators - used in cpu_cache_flush and cpu_cache_invalidate
 */

#define CPU_CACHE_NO_CACHE		0x0
#define	CPU_CACHE_DATA_CACHE		0x1
#define	CPU_CACHE_INSTRUCTION_CACHE	0x2	
#define	CPU_CACHE_ALL_CACHE		0x3

/*
 * Cache modes used in cpu_cache_info, cpu_cache_set and cpu_cache_attributes
*/

#define	CPU_CACHE_MODE_WRITETHROUGH		0x0
#define	CPU_CACHE_MODE_COPYBACK			0x20
#define	CPU_CACHE_MODE_INHIBIT_SERIALIZED	0x40
#define	CPU_CACHE_MODE_INHIBIT_NON_SERIALIZED	0x60

/*
 * MMU protection modes used in cpu_mmu_get_attributes,
 *		cpu_mmu_set_attriburtes
 */

#define	CPU_MMU_MODE_KERNEL		0x2000
#define	CPU_MMU_MODE_USER		0x0
#define	CPU_MMU_ACCESS_NONE		0x1
#define	CPU_MMU_ACCESS_READ_ONLY	0x4
#define	CPU_MMU_ACCESS_READ_WRITE	0x0

/*
 * MMU support configuration used in cpu_mmu_info
 */
#define	CPU_MMU_REGISTER		0x1
#define	CPU_MMU_PAGE_TABLE		0x2

/*
 * MMU register types for register implementation. used
 * 	by mmu get and set attributes
 */

#define CPU_MMU_REG_INSTRUCTION		0x1
#define CPU_MMU_REG_DATA		0x2

#ifdef __cplusplus
}
#endif

#endif /* _CPU_CACHE_MMU_ */