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📄 ramstart.s

📁 一个用Sansung s3c44b0x arm7控制ide硬盘的例子
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#/*************************************************************************/
#/*                                                                       */
#/*     FILE                                        VERSION               */
#/*                                                                       */
#/*      ramstart.s                              S3C44B0X 1.00            */
#/*                                                                       */
#/* Project name: UCLinux Boot Loader for S3C44B0X Main board                        */
#/* Description:				                                          */
#/*	     Board initialization codes     	                              */
#/*	                    --  Configure Memory                              */
#/*                     --  Initialize Ports                              */
#/*                     --  ISR                                           */
#/*                     --  Stacks                                        */
#/*                                                                       */
#/* AUTHOR                                                                */
#/*                                                                       */
#/*      ShangJun,Liu                                                     */
#/* DATE:                                                                 */
#/*      2003-06-07                                                       */
#/*                                                                       */
#/* HISTORY                                                               */
#/*                                                                       */
#/*         NAME            DATE                    REMARKS               */
#/*         ShangJun Liu    2003-06-06 13:10                              */
#/*         ShangJun Liu    2003-10-22 08:25                              */
#/*************************************************************************/


.include "ramstart.inc"

#/*************************************************************************/
#/* Import Modules                                                        */
#/*************************************************************************/
	.extern	Image_ZI_Base
	.extern	Image_ZI_Limit
	.extern	Image_RO_Base
	.extern	Image_RO_Limit
	.extern	Image_RW_Base
	.extern Main
	.extern IsrIRQ
	
	.extern	copy_code_to_ram
 
#/*************************************************************************/
#/* Entry of target                                                       */
#/*************************************************************************/
#		ENTRY
__entry :
		b       ResetHandler                /* Reset vector          */
		b       HandlerUndef                /* Undefined instruction */
		b       HandlerSWI		            /* SWI                   */
		b       HandlerPabort        		/* Prefetch abort        */
		b       HandlerDabort          		/* Data abort            */
		b       .                    		/* Address exception     */
		b       HandlerIRQ           		/* IRQ                   */
		@b       IsrIRQ           		/* IRQ                   */
		@LDR     pc, =IsrIRQ
		b		HandlerFIQ           		/* FIQ                   */
#/*************************************************************************/
#/* Entry of FIQ interrupt                                                */
#/*************************************************************************/
HandlerFIQ:
        sub     sp,sp,#4		
        stmfd   sp!,{r0}		
        ldr     r0,=HandleFIQ	
        ldr     r0,[r0]			
        str     r0,[sp,#4]		
        ldmfd   sp!,{r0,pc}		

#/*************************************************************************/
#/* Entry of IRQ interrupt                                                */
#/*************************************************************************/
HandlerIRQ:
        sub     sp,sp,#4
        stmfd   sp!,{r0}
        ldr     r0,=HandleIRQ
        ldr     r0,[r0]			
        str     r0,[sp,#4]
        ldmfd   sp!,{r0,pc}

#/*************************************************************************/
#/* Entry of Undefined instruction interrupt                              */
#/*************************************************************************/
HandlerUndef:
        sub     sp,sp,#4
        stmfd   sp!,{r0}		
        ldr     r0,=HandleUndef
        ldr     r0,[r0]
        str     r0,[sp,#4]
        ldmfd   sp!,{r0,pc}		

#/*************************************************************************/
#/* Entry of SWI interrupt                                                */
#/*************************************************************************/
HandlerSWI:
        sub     sp,sp,#4
        stmfd   sp!,{r0}
        ldr     r0,=HandleSWI
        ldr     r0,[r0]			
        str     r0,[sp,#4]
        ldmfd   sp!,{r0,pc}

#/*************************************************************************/
#/* Entry of Data abort interrupt                                         */
#/*************************************************************************/
HandlerDabort:
        sub     sp,sp,#4
        stmfd   sp!,{r0}		
        ldr     r0,=HandleDabort
        ldr     r0,[r0]
        str     r0,[sp,#4]
        ldmfd   sp!,{r0,pc}		

#/*************************************************************************/
#/* Entry of Prefetch abort interrupt                                      */
#/*************************************************************************/
HandlerPabort:
        sub     sp,sp,#4
        stmfd   sp!,{r0}
        ldr     r0,=HandlePabort
        ldr     r0,[r0]			
        str     r0,[sp,#4]
        ldmfd   sp!,{r0,pc}
        
#/*************************************************************************/
#/* Entry of reset vector interrupt                                       */
#/*************************************************************************/
ResetHandler :
#/*************************************************************************/
#/*                                                                       */
#/* FUNCTION                                                              */
#/*                                                                       */
#/*      main_entry                                                       */
#/*                                                                       */
#/* DESCRIPTION                                                           */
#/*                                                                       */
#/*      This function is the entry function of target                    */
#/*                                                                       */
#/*             -    	HardWare Initialization                           */
#/*             -       Configuration Port control registers              */
#/*             -       Set clock control registers                       */
#/*             -       Set memory control registers (every CS control)   */
#/*             -       init stack                                        */
#/*             -       Set memory control registers (every CS control)   */
#/*             -       Clear the un-initialized global and static        */
#/*                         C data areas                                  */
#/*             -       Move the initialized global and initialized       */
#/*                         C data areas                                  */
#/*             -       Initialize the vector table                       */
#/*             -       Jump to Main function                             */
#/*                                                                       */
#/* AUTHOR                                                                */
#/*                                                                       */
#/*      ShangJun,Liu                                                     */
#/* DATE:                                                                 */
#/*      2003-06-05                                                       */
#/* CALLED BY                                                             */
#/*                                                                       */
#/*                                                                       */
#/* CALLS                                                                 */
#/*                                                                       */
#/*      none                                                             */
#/*                                                                       */
#/* INPUTS                                                                */
#/*                                                                       */
#/*      None                                                             */
#/*                                                                       */
#/* OUTPUTS                                                               */
#/*                                                                       */
#/*      None                                                             */
#/*                                                                       */
#/* HISTORY                                                               */
#/*                                                                       */
#/*         NAME            DATE                    REMARKS               */
#/*                                                                       */
#/*                                                                       */
#/*************************************************************************/
#VOID    main_entry(void)
#{
	.global	main_entry
main_entry :	

	/*
	MOV     V1, #0
	MOV     V8, #0
	MOV     wr, #0
	MOV     sb, #0
	MOV     sl, #0
	*/

#
# Disable interrupt and switch to supervisor mode
#
	MRS		a1,CPSR				    /*; Pickup current CPSR*/
	BIC		a1,a1,#MODE_MASK		/*; Clear the mode bits*/
	ORR		a1,a1,#SUP_MODE			/*; Set the supervisor mode bits*/
	ORR		a1,a1,#LOCKOUT			/*; Insure IRQ and FIQ intr are locked out*/
	MSR		CPSR_cxsf,a1			/*; Setup the new CPSR*/
#
# HardWare Initialization.
# disable all interrupt
#
   	ldr    r0,=INTCON	    /*#Interrupt control register. */
    ldr    r1,=0x07         /*#non-vectored mode,disable IRQ,disable FIQ.  */		
    str    r1,[r0]

   	ldr    r0,=INTMSK	    /*#Interrupt MASK register. */
    ldr    r1,=0x07ffffff   /*#disable all(30) interrupt sources.*/  		
    str    r1,[r0]


    ldr    r0,=WTCON	    /*#watch dog disable*/ 
    ldr    r1,=0x0 		
    str    r1,[r0]

    ldr    r0,=SYSCFG	    /*#enable writer buffer, full cache enable, stall disable */
    ldr    r1,=0xE           		
    str    r1,[r0]

    ldr    r0,=NCACHBE0	    /*#non cacheable area control*/
    ldr    r1,=0xb0000000   /*#bank0,1,2,3,4,5 area*/           		
    str    r1,[r0]
    
    ldr    r0,=NCACHBE1	    /*#non cacheable area control*/
    ldr    r1,=0xc032c000   
    str    r1,[r0]
   

# just start to change SW code from here, according to samsung demo board.
    #****************************************************
    #*	Configuration Port control registers		    * 	
    #****************************************************

    #==== PORT A GROUP ====
    #ADDR24 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR0		      
    #     1,     1,	    1,     1,     1,     1,     1,	   1,     1,    1
	ldr	r1,=rPCONA
	ldr	r0,=0x3ff
	str	r0,[r1]

    #==== PORT B GROUP ====
    #nGCS0 - FLASH
    #nGCS1 - 74HC244 AND 74HC273
    #nGCS2 - CS8900A
    #nGCS3 - PDIUSBD12

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