tl16c550c_reg_mcu.h

这是我编一个DSP的USP的程序 调试通过

/*		FIFO and shift register are both empty.	                     */
/*		                                                             */
/*THRE	This bit is the THRE indicator. THRE is set when the THR is  */
/*		empty, indicating that the ACE is ready to accept a new      */
/*		character. If the THRE interrupt is enabled when THRE is     */
/*		set, an interrupt is generated. THRE is set when the         */
/*		contents of the THR are transferred to the TSR. THRE is      */
/*		cleared concurrent with the loading of the THR by the CPU.   */
/*		In the FIFO mode, THRE is set when the transmit FIFO is      */
/*		empty; it is cleared when at least one byte is written to the*/
/*		transmit FIFO.			                                     */
/*		                                                             */
/*BI	This bit is the break interrupt (BI) indicator. When BI is   */
/*		set, it indicates that the received data input was held low  */
/*		for longer than a full-word transmission time. A full-word   */
/*		transmission time is defined as the total time to transmit   */
/*		the start, data, parity, and stop bits. BI is cleared every  */
/*		time the CPU reads the contents of the LSR. In the FIFO mode,*/ 
/*		this error is associated with the particular character in the*/ 
/*		FIFO to which it applies. This error is revealed to the CPU  */
/*		when its associated character is at the top of the FIFO. When*/ 
/*		a break occurs, only one 0 character is loaded into the FIFO.*/ 
/*		The next character transfer is enabled after SIN goes to the */
/*		marking state for at least two RCLK samples and then receives*/ 
/*		the next valid start bit.		                             */
/*		                                                             */
/*FE	This bit is the framing error (FE) indicator. When FE is set,*/ 
/*		it indicates that the received character did not have a valid*/
/*		(set) stop bit. FE is cleared every time the CPU reads the   */
/*		contents of the LSR. In the FIFO mode, this error is         */
/*		associated with the particular character in the FIFO to which*/ 
/*		it applies. This error is revealed to the CPU when its       */
/*		associated character is at the top of the FIFO. The ACE tries*/ 
/*		to resynchronize after a framing error. To accomplish this,  */
/*		it is assumed that the framing error is due to the next start*/
/*		bit. The ACE samples this start bit twice and then accepts   */
/*		the input data.                                              */
/*		                                                             */
/*PE	This bit is the parity error (PE) indicator. When PE is set, */
/*		it indicates that the parity of the received data character  */
/*		does not match the parity selected in the LCR (bit 4). PE is */
/*		cleared every time the CPU reads the contents of the LSR.    */
/*		In the FIFO mode, this error is associated with the          */
/*		particular character in the FIFO to which it applies. This   */
/*		error is revealed to the CPU when its associated character   */
/*		is at the top of the FIFO.	                                 */
/*		                                                             */
/*OE	This bit is the overrun error (OE) indicator. When OE is set,*/
/*		it indicates that before the character in the RBR was read,  */
/*		it was overwritten by the next character transferred into    */
/*		the register. OE is cleared every time the CPU reads the     */
/*		contents of the LSR. If the FIFO mode data continues to fill */
/*		the FIFO beyond the trigger level, an overrun error occurs   */
/*		only after the FIFO is full and the next character has been  */
/*		completely received in the shift register. An overrun error  */
/*		is indicated to the CPU as soon as it happens. The character */
/*		in the shift register is overwritten, but it is not          */
/*		transferred to the FIFO.								     */																																																																																																																																																																																																																	
/*		                                                             */
/*DR	This bit is the data ready (DR) indicator for the receiver.  */
/*		DR is set whenever a complete incoming character has been    */
/*		received and transferred into the RBR or the FIFO. DR is     */
/*		cleared by reading all of the data in the RBR or the FIFO.   */
/*                                                                   */
/*===================================================================*/

	
#define TL16C550C_LSR_RCVRE		(1<<7)	
#define TL16C550C_LSR_TEMT		(1<<6)	
#define TL16C550C_LSR_THRE		(1<<5)	
#define TL16C550C_LSR_BI		(1<<4)	
#define TL16C550C_LSR_FE		(1<<3)	
#define TL16C550C_LSR_PE		(1<<2)	
#define TL16C550C_LSR_OE		(1<<1)	
#define TL16C550C_LSR_DR		(1<<0)
	
#define TL16C550C_LSR_H		(TL16C550C_LSR_RCVRE | TL16C550C_LSR_TEMT | TL16C550C_LSR_THRE | TL16C550C_LSR_BI)	
#define TL16C550C_LSR_L		(TL16C550C_LSR_FE | TL16C550C_LSR_PE | TL16C550C_LSR_OE | TL16C550C_LSR_DR)	
#define TL16C550C_LSR		(TL16C550C_LSR_H | TL16C550C_LSR_L)

	

/*===================================================================*/
/*                                                                   */
/*       			 Modem Status Register(MSR)                      */
/*                                                                   */
/*===================================================================*/
/*                                                                   */
/*                                                                   */
/* --------------------------------------------------                */
/*|  7  |  6 |  5  |  4  |  3   |   2  |  1   |  0   |               */
/* --------------------------------------------------                */
/*| DCD | RI | DSR | CTS | dDCD | TERI | dDSR | dCTS |               */
/* --------------------------------------------------                */
/*                                                                   */
/*                                                                   */
/*DCD	This bit is the complement of the data carrier detect (DCD)  */
/*	input. When the ACE is in the diagnostic test mode               */
/*	(LOOP [MCR4] = 1), this bit is equal to the MCR bit 3 (OUT2).    */
/*                                                                   */
/*RI	This bit is the complement of the ring indicator (RI) input. */
/*	When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1),   */
/*	this bit is equal to the MCR bit 2 (OUT1).                       */
/*                                                                   */
/*DSR	This bit is the complement of the data set ready (DSR) input.*/ 
/*	When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1),   */
/*	this bit is equal to the MCR bit 0 (DTR).	                     */
/*	                                                                 */
/*CTS	This bit is the complement of the clear-to-send (CTS) input. */
/*	When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1),   */
/*	this bit is equal to the MCR bit 1 (RTS).						 */
/*	                                                                 */
/*dDCD	This bit is the change in data carrier detect (dDCD)         */
/*		indicator. .DCD indicates that the DCD input to the chip     */
/*		has changed state since the last time it was read by the     */
/*		CPU. When dDCD is set and the modem status interrupt is      */
/*		enabled, a modem status interrupt is generated.              */
/*		                                                             */
/*TERI	This bit is the trailing edge of the ring indicator (TERI)   */
/*		detector. TERI indicates that the RI input to the chip       */
/*		has changed from a low to a high level. When TERI is set     */
/*		and the modem status interrupt is enabled, a modem status    */
/*		interrupt is generated.                                      */
/*		                                                             */
/*dDSR	This bit is the change in data set ready (dDSR) indicator.   */
/*		dDSR indicates that the DSR input has changed state since    */
/*		the last time it was read by the CPU. When .DSR is set and   */
/*		the modem status interrupt is enabled, a modem status        */
/*		interrupt is generated.                                      */
/*		                                                             */
/*dCTS	This bit is the change in clear-to-send (dCTS) indicator.    */
/*		dCTS indicates that the CTS input has changed state since    */
/*		the last time it was read by the CPU. When dCTS is set       */
/*		(autoflow control is not enabled and the modem status        */
/*		interrupt is enabled), a modem status interrupt is           */
/*		generated. When autoflow control is enabled (dCTS is         */
/*		cleared), no interrupt is generated.						 */																
/*                                                                   */
/*===================================================================*/



#define TL16C550C_MSR_DCD		(0<<7)
#define TL16C550C_MSR_RI		(0<<6)
#define TL16C550C_MSR_DSR		(0<<5)
#define TL16C550C_MSR_CTS		(0<<4)
#define TL16C550C_MSR_dDCD		(0<<3)
#define TL16C550C_MSR_TERI		(0<<2)
#define TL16C550C_MSR_dDSR		(0<<1)
#define TL16C550C_MSR_dCTS		(0<<0)

#define TL16C550C_MSR_H		(TL16C550C_MSR_DCD | TL16C550C_MSR_RI | TL16C550C_MSR_DSR | TL16C550C_MSR_CTS)
#define TL16C550C_MSR_L		(TL16C550C_MSR_dDCD | TL16C550C_MSR_TERI | TL16C550C_MSR_dDSR | TL16C550C_MSR_dCTS)
#define TL16C550C_MSR		(TL16C550C_MSR_H | TL16C550C_MSR_L)



/*==================================================================*/
/*                                                                  */
/*          TL16C550C Register Address                              */
/*																	*/
/*==================================================================*/

/* IO address for C6000 system
#define	TL16C550C_RBR_ADDR	(char *)0x0B0000000
#define	TL16C550C_THR_ADDR	(char *)0x0B0000000
#define	TL16C550C_DLL_ADDR	(char *)0x0B0000000

#define	TL16C550C_IER_ADDR	(char *)0x0B0000004
#define	TL16C550C_DLM_ADDR	(char *)0x0B0000004

#define	TL16C550C_IIR_ADDR	(char *)0x0B0000008
#define	TL16C550C_FCR_ADDR	(char *)0x0B0000008

#define	TL16C550C_LCR_ADDR	(char *)0x0B000000C
#define	TL16C550C_MCR_ADDR	(char *)0x0B0000010   
#define	TL16C550C_LSR_ADDR	(char *)0x0B0000014
#define	TL16C550C_MSR_ADDR	(char *)0x0B0000018      
#define	TL16C550C_SCR_ADDR	(char *)0x0B000001C
*/

unsigned ioport porta000;
unsigned ioport porta001;
unsigned ioport porta002;
unsigned ioport porta003;
unsigned ioport porta004;
unsigned ioport porta005;
unsigned ioport porta006;
unsigned ioport porta007;

#define	TL16C550C_RBR_ADDR	porta000
#define	TL16C550C_THR_ADDR	porta000
#define	TL16C550C_DLL_ADDR	porta000

#define	TL16C550C_IER_ADDR	porta001
#define	TL16C550C_DLM_ADDR	porta001

#define	TL16C550C_IIR_ADDR	porta002
#define	TL16C550C_FCR_ADDR	porta002

#define	TL16C550C_LCR_ADDR	porta003
#define	TL16C550C_MCR_ADDR	porta004                     
#define	TL16C550C_LSR_ADDR	porta005                  
#define	TL16C550C_MSR_ADDR	porta006                        
#define	TL16C550C_SCR_ADDR	porta007