tl16c550c_reg_mcu.h

这是我编一个DSP的USP的程序 调试通过

#define TL16C550C_FCR_RFRST		(0<<1)
#define TL16C550C_FCR_FIFOEN	(1<<0)

#define TL16C550C_FCR_H		(TL16C550C_FCR_RTRI | TL16C550C_FCR_RSV | TL16C550C_FCR_DMAMS)
#define TL16C550C_FCR_L		(TL16C550C_FCR_TFRST | TL16C550C_FCR_RFRST | TL16C550C_FCR_FIFOEN)
#define TL16C550C_FCR		(TL16C550C_FCR_H | TL16C550C_FCR_L)	



/*==================================================================*/
/*																	*/
/*				Line Control Register(LCR							*/
/*																	*/
/*==================================================================*/	
/*																	*/
/*																	*/
/* ------------------------------------------------                 */
/*|   7  |  6 |  5 |  4  |  3  |  2  |   1  |  0   |                */
/* ------------------------------------------------                 */
/*| DLAB | BC | SP | EPS | PEN | STB | WLS1 | WLS0 | 		        */
/* ------------------------------------------------                 */
/*                                                                  */
/*                                                                  */
/*DLAB	This bit is the divisor latch access bit (DLAB). Bit 7 must */
/*		be set to access the divisor latches of the baud generator  */
/*		during a read or write. Bit 7 must be cleared during a read */
/*		or write to access the receiver buffer, the THR, or the IER.*/
/*																	*/
/*BC	This bit is the break control bit. Bit 6 is set to force a  */
/*		break condition; i.e., a condition where SOUT is forced to  */
/*		the spacing (cleared) state. When bit 6 is cleared, the 	*/
/*		break condition is disabled and has no affect on the        */
/*		transmitter logic; it only effects SOUT.					*/
/*																	*/
/*SP	This bit is the stick parity bit. When bits 3, 4, and 5 are */
/*		set, the parity bit is transmitted and checked as cleared.  */
/*		When bits 3 and 5 are set and bit 4 is cleared, the parity  */
/*		bit is transmitted and checked as set. If bit 5 is cleared, */
/*      stick parity is disabled.                                   */
/*																	*/
/*EPS	This bit is the even parity select bit. When parity is 		*/
/*		enabled (bit 3 is set) and bit 4 is set even parity (an even*/
/*		number of logic 1s in the data and parity bits) is selected.*/
/*		When parity is enabled and bit 4 is cleared, odd parity (an */
/*		odd number of logic 1s) is selected.						*/
/*																	*/
/*PEN	This bit is the parity enable bit. When bit 3 is set, a 	*/
/*		parity bit is generated in transmitted data between the last*/
/*		data word bit and the first stop bit. In received data, if  */
/*		bit 3 is set, parity is checked. When bit 3 is cleared, no  */
/*		parity is generated or checked.                             */
/*       															*/
/*STB	This bit specifies either one, one and one-half, or two stop*/
/*		bits in each transmitted character. When bit 2 is cleared,  */
/*		one stop bit is generated in the data. When bit 2 is set,   */
/*		the number of stop bits generated is dependent on the word  */
/*		length selected with bits 0 and 1. The receiver clocks only */
/* 		the first stop bit regardless of the number of stop bits    */
/*		selected. The number of stop bits generated in relation to  */
/*		word length and bit 2 are shown in Table.                   */
/*           -------------------------------                        */
/*			| STB | WORD LENGTH | STOP BITS |                       */
/*           -------------------------------                        */
/*          |  0  | Any word len|     1     |                       */
/*           -------------------------------                        */
/*          |  1  |     5bits   |   1 1/2   |                       */
/*           -------------------------------                        */
/*          |  1  |     6bits   |     2     |                       */
/*           -------------------------------                        */
/*          |  1  |     7bits   |     2     |                       */
/*           -------------------------------                        */
/*          |  1  |     8bits   |     2     |                       */
/*           -------------------------------                        */
/*         															*/
/*WLS	These two bits specify the number of bits in each 			*/
/*		transmitted or received serial character. These bits are    */
/*		encoded as shown in Table.									*/
/*          -----------------------------                           */
/*         | BIT 1 | BIT 0 | WORD LENGTH |                          */
/*			-----------------------------                           */
/*		   |   0   |   0   |    5bits    |                          */
/*          -----------------------------                           */
/*		   |   0   |   1   |    6bits    |                          */
/*          -----------------------------                           */
/*		   |   1   |   0   |    7bits    |                          */
/*          -----------------------------                           */
/*		   |   1   |   1   |    8bits    |                          */
/*          -----------------------------                           */
/*         															*/
/*==================================================================*/


#define	TL16C550C_LCR_DLAB		(0<<7)
#define	TL16C550C_LCR_DLAB_ON	(1<<7)
#define	TL16C550C_LCR_BC		(0<<6)
#define	TL16C550C_LCR_SP		(0<<5)
#define	TL16C550C_LCR_EPS		(0<<4)
#define	TL16C550C_LCR_PEN_ON	(1<<3)
#define	TL16C550C_LCR_PEN		(0<<3)
#define	TL16C550C_LCR_STB		(0<<2)
#define	TL16C550C_LCR_WLS		(3<<0)

#define	TL16C550C_LCR_H		(TL16C550C_LCR_DLAB | TL16C550C_LCR_BC | TL16C550C_LCR_SP | TL16C550C_LCR_EPS)
#define	TL16C550C_LCR_L		(TL16C550C_LCR_PEN | TL16C550C_LCR_STB | TL16C550C_LCR_WLS)
#define	TL16C550C_LCR		(TL16C550C_LCR_H | TL16C550C_LCR_L)

#define	TL16C550C_LCR_Baud_H (TL16C550C_LCR_DLAB_ON | TL16C550C_LCR_BC | TL16C550C_LCR_SP | TL16C550C_LCR_EPS)
#define	TL16C550C_LCR_Baud_L (TL16C550C_LCR_PEN_ON | TL16C550C_LCR_STB | TL16C550C_LCR_WLS)
#define	TL16C550C_LCR_Baud	 (TL16C550C_LCR_Baud_H | TL16C550C_LCR_Baud_L)



/*==================================================================*/
/*																	*/
/*            Modem Control Register(MCR)                           */
/*                                                                  */
/*==================================================================*/
/*																	*/
/*																	*/
/* --------------------------------------------                     */
/*| 7.6 |  5  |  4   |  3   |   2  |  1  |  0  |                    */
/* --------------------------------------------                     */
/*| RSV | AFE | LOOP | OUT2 | OUT1 | RTS | DTR |                    */
/* --------------------------------------------                     */
/*																	*/
/*																	*/
/*AFE	This bit (AFE) is the autoflow control enable. When set, the*/
/*		autoflow control as described in the detailed description is*/
/*		enabled.													*/
/*		The ACE flow can be configured by programming bits 1 & 5 of */
/*		the MCR as shown in Table.									*/
/*	       ---------------------------------------------        	*/
/*        |	AFE | RTS | ACE FLOW CONFIGURATION          |           */
/*         ---------------------------------------------            */
/*        |  1  |  1  | Auto-/RTS and auto-/CTS enabled |           */
/*         ---------------------------------------------            */
/*		  |  1  |  0  | Auto-/CTS only enabled          |           */
/*         ---------------------------------------------            */
/*																	*/
/*LOOP	This bit (LOOP) provides a local loop back feature for 		*/
/*		diagnostic testing of the ACE. When LOOP is set, the        */
/*		following occurs:											*/
/*			--- The transmitter SOUT is set high.                   */
/*			--- The receiver SIN is disconnected.                   */
/*			--- The output of the TSR is looped back into the 		*/
/*				receiver shift register input.                      */
/*			--- The four modem control inputs (CTS, DSR, DCD, and   */
/*				RI) are disconnected.                               */
/*			--- The four modem control outputs (DTR, RTS, OUT1, and */
/*				OUT2) are internally connected to the four modem    */
/*				control inputs.                                     */
/*			--- The four modem control outputs are forced to the    */
/*				inactive (high) levels.                             */
/*				                                                    */
/*OUT2	This bit (OUT2) controls OUT2, a user-designated output     */
/*		signal.	                                                    */
/*		                                                            */
/*OUT1	This bit (OUT1) controls OUT1, a user-designated output     */
/*		signal.	                                                    */
/*		                                                            */
/*RTS	This bit (RTS) controls the RTS output.   	                */
/*                                                                  */
/*DTR	This bit (DTR) controls the DTR output.	   	                */
/*																	*/
/*		When any of bits 0 through 3 are set, the associated output */
/*		is forced low. When any of these bits are cleared, the      */
/*		associated output is forced high.							*/
/*																	*/	
/*==================================================================*/


#define TL16C550C_MCR_RSV		(0<<6)
#define TL16C550C_MCR_AFE		(0<<5)
#define TL16C550C_MCR_LOOP		(0<<4)
#define TL16C550C_MCR_OUT2		(0<<3)
#define TL16C550C_MCR_OUT1		(0<<2)
#define TL16C550C_MCR_RTS		(0<<1)
#define TL16C550C_MCR_DTR		(0<<0)


#define TL16C550C_MCR_H		(TL16C550C_MCR_RSV | TL16C550C_MCR_AFE | TL16C550C_MCR_LOOP | TL16C550C_MCR_OUT2)
#define TL16C550C_MCR_L		(TL16C550C_MCR_OUT1 | TL16C550C_MCR_RTS | TL16C550C_MCR_DTR)
#define TL16C550C_MCR		(TL16C550C_MCR_H | TL16C550C_MCR_DTR)


/*===================================================================*/
/*       															 */
/*					Line Status Register(LSR)                        */
/*       															 */
/*===================================================================*/
/*       															 */
/*       														  	 */
/* ---------------------------------------------                     */
/*|   7   |   6  |   5  | 4 |  3  |  2 |  1 |  0 |                   */
/* ----------------------------------------------                    */
/*| RCVRE | TEMT | THRE | BI | FE | PE | OE | DR |                   */
/* ----------------------------------------------                    */
/*       														     */
/*       															 */
/*RCVRE	In the TL16C550C mode, this bit is always cleared. In the    */
/*		TL16C450 mode, this bit is always cleared. In the FIFO mode, */
/*		LSR7 is set when there is at least one parity, framing, or   */
/*		break error in the FIFO. It is cleared when the              */
/*		microprocessor reads the LSR and there are no subsequent     */
/*		errors in the FIFO.		                                     */
/*		                                                             */
/*TEMT	This bit is the transmitter empty (TEMT) indicator. TEMT bit */
/*		is set when the THR and the TSR are both empty. When either  */
/*		the THR or the TSR contains a data character, TEMT is        */
/*		cleared. In the FIFO mode,TEMT is set when the transmitter   */