tl16c550c_reg_mcu.h

这是我编一个DSP的USP的程序 调试通过

/********************************************************************/ 
/*                                                                  */
/* Copyright 2003 by Lab140 UESTC.                                  */                                
/* All rights reserved. Property of Lab140 UESTC.                   */
/* Restricted rights to use, duplicate or disclose this code are    */
/* granted through contract.                                        */
/*                                                                  */  
/********************************************************************/
/*                                                                  */
/* FILENAME: TL16C550CReg.h                                         */
/* This file contains all register information of the TL16C550C.    */
/* which can be used in the UART initialization program.            */                                          
/* Lastest modified by J.R.Lin on July,21st,2003.                   */
/*                                                                  */
/********************************************************************/



/*==================================================================*/
/*                                                                  */
/*                      Register  Selection                         */
/*                                                                  */
/*==================================================================*/


/* -----------------------------------------------------------------------------------    */
/*|	DLAB | A2 |	A1 | A0	|			REGISTER                                          |   */
/* -----------------------------------------------------------------------------------    */
/*|   0  | L  | L  | L  | Receiver buffer (read), transmitter holding register (write)|   */
/* -----------------------------------------------------------------------------------    */
/*|   0  | L  | L  | H  | Interrupt enable register                                   |   */
/* -----------------------------------------------------------------------------------    */
/*|   X  | L  | H  | L  | Interrupt identification register (read only)               |   */
/* -----------------------------------------------------------------------------------    */
/*|   X  | L  | H  | L  | FIFO control register (write)                               |   */
/* -----------------------------------------------------------------------------------    */
/*|   X  | L  | H  | H  | Line control register                                       |   */
/* -----------------------------------------------------------------------------------    */
/*|   X  | H  | L  | L  | Modem control register                                      |   */
/* -----------------------------------------------------------------------------------    */
/*|   X  | H  | L  | H  | Line status register                                        |   */
/* -----------------------------------------------------------------------------------    */
/*|   X  | H  | H  | L  | Modem status register                                       |   */
/* -----------------------------------------------------------------------------------    */
/*|   X  | H  | H  | H  | Scratch register                                            |   */
/* -----------------------------------------------------------------------------------    */
/*|   1  | L  | L  | L  | Divisor latch (LSB)                                         |   */
/* -----------------------------------------------------------------------------------    */
/*|   1  | L  | L  | H  | Divisor latch (MSB)                                         |   */
/* -----------------------------------------------------------------------------------    */
                                                                                          
                                                                                          
                                                                                          
/*==================================================================*/                    
/*                                                                  */                    
/*                Interrupt Enable Register(IER)                    */
/*                                                                  */
/*==================================================================*/
/*                                                                  */
/*                                                                  */
/* -------------------------------------                            */
/*| 7...4 |   3   |   2  |   1   |  0   |                           */
/* -------------------------------------                            */
/*|  RSV  | EDSSI | ELSI | ETBEI | ERBI |                           */
/* -------------------------------------                            */
/*                                                                  */
/*                                                                  */ 
/*ESSSI		When set, this bit enables the modem status interrupt.  */
/*																	*/
/*ELSI		When set, this bit enables the receiver line status     */
/*				interrupt.											*/
/*																	*/
/*ETBEI		When set, this bit enables the THRE interrupt.			*/
/*																	*/
/*ERBI		When set, this bit enables the received data available  */
/*				interrupt.											*/
/*																	*/
/*==================================================================*/

#define	TL16C550C_IER_RSV1		(0<<4)
#define	TL16C550C_IER_EDSSI     (0<<3)
#define	TL16C550C_IER_ELSE		(0<<2)
#define	TL16C550C_IER_ETBEI		(0<<1)
#define	TL16C550C_IER_ERBI		(1<<0)

#define TL16C550C_IER	(TL16C550C_IER_RSV1 | TL16C550C_IER_EDSSI | TL16C550C_IER_ELSE | TL16C550C_IER_ETBEI | TL16C550C_IER_ERBI)



/*==================================================================*/
/*                                                                  */
/*			Interrupt Ident. Register(IIR, read only)               */
/*                                                                  */
/*==================================================================*/
/*																	*/
/*																	*/
/* ---------------------------------------------------------------- */
/*|    7    |    6    | 5.4 |    3    |    2    |    1    |   0    |*/
/* ---------------------------------------------------------------- */
/*| FIFO E1 | FIFO E0 | RSV | INT ID3 | INT ID2 | INT ID1 | INT PED|*/
/* ---------------------------------------------------------------- */
/*																	*/
/*																	*/  
/*FIFO_E1,0	These bits are always cleared in TL16C450 mode. They are*/
/*			set when bit 0 of the FIFO control register is set.     */
/*																	*/
/*INT_ID3	This bit is always cleared in TL16C450 mode. In FIFO    */
/*			mode, bit3 is set with bit 2 to indicate that a time-out*/
/*			interrupt is pending.									*/
/*																	*/
/*INT_ID2,1	These two bits identify the highest priority interrupt  */
/*			pending													*/
/*																	*/
/*INT_PEND	This bit is used either in a hardwire prioritized or 	*/
/*			polled interrupt system. When bit 0 is cleared, an      */
/*			interrupt is pending If bit 0 is set, no interrupt is   */
/*			pending.												*/
/*																	*/
/*==================================================================*/


/*     ---------------------------------------------------------------------------        */
/*    | BIT3 | BIT2 | BIT1 | BIT0 | PRIORITY | 		INTERRUPT TYPE	              |       */
/*     ---------------------------------------------------------------------------        */
/*    |  0   |   0  |   0  |   1  |   None   |     		None     	              |       */
/*     ---------------------------------------------------------------------------        */
/*    |  0   |   1  |   1  |   0  |    1     | Receiver line status	              |       */
/*     ---------------------------------------------------------------------------        */
/*    |  0   |   1  |   0  |   0  |    2     | Received data available            |       */
/*     ---------------------------------------------------------------------------        */
/*    |  1   |   1  |   0  |   0  |    2     | Character time-out indication      |       */
/*     ---------------------------------------------------------------------------        */
/*    |  0   |   0  |   1  |   0  |    3     | Transmitter holding register empty |       */
/*     ---------------------------------------------------------------------------        */
/*    |  0   |   0  |   0  |   0  |    4     | Modem status	                      |       */
/*     ---------------------------------------------------------------------------        */


#define	TL16C550C_IIR_FIFO_E1		(0<<7)
#define	TL16C550C_IIR_FIFO_E0		(0<<6)
#define	TL16C550C_IIR_RSV			(0<<4)
#define	TL16C550C_IIR_INT_ID3		(0<<3)
#define	TL16C550C_IIR_INT_ID2		(0<<2)
#define	TL16C550C_IIR_INT_ID1		(0<<1)
#define	TL16C550C_IIR_INT_PEND		(0<<0)

#define UartReceiveInt              (1<<2)
#define UartTransInt                (1<<1)

#define	TL16C550C_IIR_H	(TL16C550C_IIR_FIFO_E1 | TL16C550C_IIR_FIFO_E0 | TL16C550C_IIR_RSV | TL16C550C_IIR_INT_ID3)
#define	TL16C550C_IIR_L (TL16C550C_IIR_INT_ID2 | TL16C550C_IIR_INT_ID1 | TL16C550C_IIR_INT_PEND)
#define	TL16C550C_IIR	(TL16C550C_IIR_H | TL16C550C_IIR_L)



/*==================================================================*/
/*																	*/
/*		FIFO Control Register(FCR, write only)                      */
/*																	*/
/*==================================================================*/
/*																	*/
/*																	*/
/* -------------------------------------------------------------	*/
/*|        7..6      | 5.4 |         3       |        2         |	*/
/* -------------------------------------------------------------	*/
/*| Receiver Trigger | RSV | DMA Mode Select | Transmit FIFO Rst|	*/
/* -------------------------------------------------------------    */
/*                                                                  */
/* ---------------------------------                                */
/*| Receiver FIFO Rst | FIFO Enable |								*/
/* ---------------------------------								*/
/*																	*/
/*RTRI1		These two bits set the trigger level for the receiver 	*/
/*			FIFO interrupt.											*/
/*				--------------------------------------------------- */
/*			   | BIT 7 | BIT 6 | RECEIVER FIFO TRIGGER LEVEL(BYTES)|*/
/*			    --------------------------------------------------- */
/*			   |   0   |   0   |         		01                 |*/
/*				--------------------------------------------------- */
/*			   |   0   |   1   |         		04                 |*/
/*				--------------------------------------------------- */
/*			   |   1   |   0   |         		08                 |*/
/*				--------------------------------------------------- */
/*			   |   1   |   1   |         		14                 |*/
/*				--------------------------------------------------- */
/*																	*/
/*DMAMS		When FCR0 is set, setting FCR3 causes RXRDY and TXRDY to*/
/*			change from level 0 to level 1.							*/
/*																	*/
/*TFRST		This bit, when set, clears all bytes in the transmit 	*/
/*			FIFO and clears its counter. The shift register is not  */
/*			cleared. The 1 that is written to this bit position is 	*/
/*			self clearing.                                          */
/*																	*/
/*RFRST		This bit, when set, clears all bytes in the receiver 	*/
/*			FIFO and clears its counter. The shift register is not  */
/*			cleared. The 1 that is written to this bit position is 	*/
/*			self clearing.											*/
/*																	*/
/*FIFOEN	This bit, when set, enables the transmitter and receiver*/
/*			FIFOs. Bit 0 must be set when other FCR bits are written*/
/*			to or they are not programmed. Changing this bit clears */
/*			the FIFOs.												*/
/*																	*/
/*==================================================================*/

#define TL16C550C_FCR_RTRI		(0<<6)
#define TL16C550C_FCR_RSV		(0<<4)
#define TL16C550C_FCR_DMAMS		(0<<3)
#define TL16C550C_FCR_TFRST		(0<<2)