at91rm9200_tc.h

arch-at91rm9200

/* linux/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
 * 
 * Hardware definition for the tc peripheral in the ATMEL at91rm9200 processor
 * 
 * Generated  01/09/2006 (16:49:36) AT91 SW Application Group from RTC_1245D V1.3
 * 
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 * 
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * You should have received a copy of the  GNU General Public License along
 * with this program; if not, write  to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */


#ifndef __AT91RM9200_TC_H
#define __AT91RM9200_TC_H

/* -------------------------------------------------------- */
/* TC ID definitions for  AT91RM9200           */
/* -------------------------------------------------------- */
#ifndef AT91C_ID_TC0
#define AT91C_ID_TC0   	17 /**< Timer Counter 0 id */
#endif /* AT91C_ID_TC0 */
#ifndef AT91C_ID_TC1
#define AT91C_ID_TC1   	18 /**< Timer Counter 1 id */
#endif /* AT91C_ID_TC1 */
#ifndef AT91C_ID_TC2
#define AT91C_ID_TC2   	19 /**< Timer Counter 2 id */
#endif /* AT91C_ID_TC2 */
#ifndef AT91C_ID_TC3
#define AT91C_ID_TC3   	20 /**< Timer Counter 3 id */
#endif /* AT91C_ID_TC3 */
#ifndef AT91C_ID_TC4
#define AT91C_ID_TC4   	21 /**< Timer Counter 4 id */
#endif /* AT91C_ID_TC4 */
#ifndef AT91C_ID_TC5
#define AT91C_ID_TC5   	22 /**< Timer Counter 5 id */
#endif /* AT91C_ID_TC5 */

/* -------------------------------------------------------- */
/* TC Base Address definitions for  AT91RM9200   */
/* -------------------------------------------------------- */
#define AT91C_BASE_TC5       	0xFFFA4080 /**< TC5 base address */
#define AT91C_BASE_TC4       	0xFFFA4040 /**< TC4 base address */
#define AT91C_BASE_TC3       	0xFFFA4000 /**< TC3 base address */
#define AT91C_BASE_TC2       	0xFFFA0080 /**< TC2 base address */
#define AT91C_BASE_TC1       	0xFFFA0040 /**< TC1 base address */
#define AT91C_BASE_TC0       	0xFFFA0000 /**< TC0 base address */

/* -------------------------------------------------------- */
/* PIO definition for TC hardware peripheral */
/* -------------------------------------------------------- */

/* -------------------------------------------------------- */
/* Register offset definition for TC hardware peripheral */
/* -------------------------------------------------------- */
#define TC_CCR 	(0x0000) 	/**< Channel Control Register */
#define TC_CMR 	(0x0004) 	/**< Channel Mode Register (Capture Mode / Waveform Mode) */
#define TC_CV 	(0x0010) 	/**< Counter Value */
#define TC_RA 	(0x0014) 	/**< Register A */
#define TC_RB 	(0x0018) 	/**< Register B */
#define TC_RC 	(0x001C) 	/**< Register C */
#define TC_SR 	(0x0020) 	/**< Status Register */
#define TC_IER 	(0x0024) 	/**< Interrupt Enable Register */
#define TC_IDR 	(0x0028) 	/**< Interrupt Disable Register */
#define TC_IMR 	(0x002C) 	/**< Interrupt Mask Register */

/* -------------------------------------------------------- */
/* Bitfields definition for TC hardware peripheral */
/* -------------------------------------------------------- */
/* --- Register TC_CCR */
#define AT91C_TC_CLKEN        (0x1 << 0 ) /**< (TC) Counter Clock Enable Command */
#define AT91C_TC_CLKDIS       (0x1 << 1 ) /**< (TC) Counter Clock Disable Command */
#define AT91C_TC_SWTRG        (0x1 << 2 ) /**< (TC) Software Trigger Command */
/* --- Register TC_CMR */
#define AT91C_TC_CLKS         (0x7 << 0 ) /**< (TC) Clock Selection */
#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     0x0 /**< (TC) Clock selected: TIMER_DIV1_CLOCK */
#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     0x1 /**< (TC) Clock selected: TIMER_DIV2_CLOCK */
#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     0x2 /**< (TC) Clock selected: TIMER_DIV3_CLOCK */
#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     0x3 /**< (TC) Clock selected: TIMER_DIV4_CLOCK */
#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     0x4 /**< (TC) Clock selected: TIMER_DIV5_CLOCK */
#define 	AT91C_TC_CLKS_XC0                  0x5 /**< (TC) Clock selected: XC0 */
#define 	AT91C_TC_CLKS_XC1                  0x6 /**< (TC) Clock selected: XC1 */
#define 	AT91C_TC_CLKS_XC2                  0x7 /**< (TC) Clock selected: XC2 */
#define AT91C_TC_CLKS         (0x7 << 0 ) /**< (TC) Clock Selection */
#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     0x0 /**< (TC) Clock selected: TIMER_DIV1_CLOCK */
#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     0x1 /**< (TC) Clock selected: TIMER_DIV2_CLOCK */
#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     0x2 /**< (TC) Clock selected: TIMER_DIV3_CLOCK */
#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     0x3 /**< (TC) Clock selected: TIMER_DIV4_CLOCK */
#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     0x4 /**< (TC) Clock selected: TIMER_DIV5_CLOCK */
#define 	AT91C_TC_CLKS_XC0                  0x5 /**< (TC) Clock selected: XC0 */
#define 	AT91C_TC_CLKS_XC1                  0x6 /**< (TC) Clock selected: XC1 */
#define 	AT91C_TC_CLKS_XC2                  0x7 /**< (TC) Clock selected: XC2 */
#define AT91C_TC_CLKI         (0x1 << 3 ) /**< (TC) Clock Invert */
#define AT91C_TC_CLKI         (0x1 << 3 ) /**< (TC) Clock Invert */
#define AT91C_TC_BURST        (0x3 << 4 ) /**< (TC) Burst Signal Selection */
#define 	AT91C_TC_BURST_NONE                 (0x0 <<  4) /**< (TC) The clock is not gated by an external signal */
#define 	AT91C_TC_BURST_XC0                  (0x1 <<  4) /**< (TC) XC0 is ANDed with the selected clock */
#define 	AT91C_TC_BURST_XC1                  (0x2 <<  4) /**< (TC) XC1 is ANDed with the selected clock */
#define 	AT91C_TC_BURST_XC2                  (0x3 <<  4) /**< (TC) XC2 is ANDed with the selected clock */
#define AT91C_TC_BURST        (0x3 << 4 ) /**< (TC) Burst Signal Selection */
#define 	AT91C_TC_BURST_NONE                 (0x0 <<  4) /**< (TC) The clock is not gated by an external signal */
#define 	AT91C_TC_BURST_XC0                  (0x1 <<  4) /**< (TC) XC0 is ANDed with the selected clock */
#define 	AT91C_TC_BURST_XC1                  (0x2 <<  4) /**< (TC) XC1 is ANDed with the selected clock */
#define 	AT91C_TC_BURST_XC2                  (0x3 <<  4) /**< (TC) XC2 is ANDed with the selected clock */
#define AT91C_TC_CPCSTOP      (0x1 << 6 ) /**< (TC) Counter Clock Stopped with RC Compare */