at91rm9200_smc2.h

arch-at91rm9200

/* linux/include/asm-arm/arch-at91rm9200/at91rm9200_smc2.h
 * 
 * Hardware definition for the smc2 peripheral in the ATMEL at91rm9200 processor
 * 
 * Generated  01/09/2006 (16:49:36) AT91 SW Application Group from  V
 * 
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 * 
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * You should have received a copy of the  GNU General Public License along
 * with this program; if not, write  to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */


#ifndef __AT91RM9200_SMC2_H
#define __AT91RM9200_SMC2_H

/* -------------------------------------------------------- */
/* SMC2 ID definitions for  AT91RM9200           */
/* -------------------------------------------------------- */

/* -------------------------------------------------------- */
/* SMC2 Base Address definitions for  AT91RM9200   */
/* -------------------------------------------------------- */
#define AT91C_BASE_SMC2      	0xFFFFFF70 /**< SMC2 base address */

/* -------------------------------------------------------- */
/* PIO definition for SMC2 hardware peripheral */
/* -------------------------------------------------------- */
#define AT91C_PC9_A25_CFRNW 	(1 << 9) /**< Address Bus[25] /  Compact Flash Read Not Write */
#define AT91C_PC10_NCS4_CFCS 	(1 << 10) /**< Compact Flash Chip Select */
#define AT91C_PC11_NCS5_CFCE1 	(1 << 11) /**< Chip Select 5 / Compact Flash Chip Enable 1 */
#define AT91C_PC12_NCS6_CFCE2 	(1 << 12) /**< Chip Select 6 / Compact Flash Chip Enable 2 */


/* -------------------------------------------------------- */
/* Register offset definition for SMC2 hardware peripheral */
/* -------------------------------------------------------- */
#define SMC2_CSR 	(0x0000) 	/**< SMC2 Chip Select Register */

/* -------------------------------------------------------- */
/* Bitfields definition for SMC2 hardware peripheral */
/* -------------------------------------------------------- */
/* --- Register SMC2_CSR */
#define AT91C_SMC2_NWS        (0x7F << 0 ) /**< (SMC2) Number of Wait States */
#define AT91C_SMC2_WSEN       (0x1 << 7 ) /**< (SMC2) Wait State Enable */
#define AT91C_SMC2_TDF        (0xF << 8 ) /**< (SMC2) Data Float Time */
#define AT91C_SMC2_BAT        (0x1 << 12) /**< (SMC2) Byte Access Type */
#define AT91C_SMC2_DBW        (0x1 << 13) /**< (SMC2) Data Bus Width */
#define 	AT91C_SMC2_DBW_16                   (0x1 << 13) /**< (SMC2) 16-bit. */
#define 	AT91C_SMC2_DBW_8                    (0x2 << 13) /**< (SMC2) 8-bit. */
#define AT91C_SMC2_DRP        (0x1 << 15) /**< (SMC2) Data Read Protocol */
#define AT91C_SMC2_ACSS       (0x3 << 16) /**< (SMC2) Address to Chip Select Setup */
#define 	AT91C_SMC2_ACSS_STANDARD             (0x0 << 16) /**< (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */
#define 	AT91C_SMC2_ACSS_1_CYCLE              (0x1 << 16) /**< (SMC2) One cycle less at the beginning and the end of the access. */
#define 	AT91C_SMC2_ACSS_2_CYCLES             (0x2 << 16) /**< (SMC2) Two cycles less at the beginning and the end of the access. */
#define 	AT91C_SMC2_ACSS_3_CYCLES             (0x3 << 16) /**< (SMC2) Three cycles less at the beginning and the end of the access. */
#define AT91C_SMC2_RWSETUP    (0x7 << 24) /**< (SMC2) Read and Write Signal Setup Time */
#define AT91C_SMC2_RWHOLD     (0x7 << 28) /**< (SMC2) Read and Write Signal Hold Time */

#endif /* __AT91RM9200_SMC2_H */