at91rm9200_sys.h

arch-at91rm9200

#define PIOB_ISR 	(0x064C) 	/**< Interrupt Status Register */
#define PIOB_MDER 	(0x0650) 	/**< Multi-driver Enable Register */
#define PIOB_MDDR 	(0x0654) 	/**< Multi-driver Disable Register */
#define PIOB_MDSR 	(0x0658) 	/**< Multi-driver Status Register */
#define PIOB_PPUDR 	(0x0660) 	/**< Pull-up Disable Register */
#define PIOB_PPUER 	(0x0664) 	/**< Pull-up Enable Register */
#define PIOB_PPUSR 	(0x0668) 	/**< Pad Pull-up Status Register */
#define PIOB_ASR 	(0x0670) 	/**< Select A Register */
#define PIOB_BSR 	(0x0674) 	/**< Select B Register */
#define PIOB_ABSR 	(0x0678) 	/**< AB Select Status Register */
#define PIOB_OWER 	(0x06A0) 	/**< Output Write Enable Register */
#define PIOB_OWDR 	(0x06A4) 	/**< Output Write Disable Register */
#define PIOB_OWSR 	(0x06A8) 	/**< Output Write Status Register */
#define PIOC_PER 	(0x0800) 	/**< PIO Enable Register */
#define PIOC_PDR 	(0x0804) 	/**< PIO Disable Register */
#define PIOC_PSR 	(0x0808) 	/**< PIO Status Register */
#define PIOC_OER 	(0x0810) 	/**< Output Enable Register */
#define PIOC_ODR 	(0x0814) 	/**< Output Disable Registerr */
#define PIOC_OSR 	(0x0818) 	/**< Output Status Register */
#define PIOC_IFER 	(0x0820) 	/**< Input Filter Enable Register */
#define PIOC_IFDR 	(0x0824) 	/**< Input Filter Disable Register */
#define PIOC_IFSR 	(0x0828) 	/**< Input Filter Status Register */
#define PIOC_SODR 	(0x0830) 	/**< Set Output Data Register */
#define PIOC_CODR 	(0x0834) 	/**< Clear Output Data Register */
#define PIOC_ODSR 	(0x0838) 	/**< Output Data Status Register */
#define PIOC_PDSR 	(0x083C) 	/**< Pin Data Status Register */
#define PIOC_IER 	(0x0840) 	/**< Interrupt Enable Register */
#define PIOC_IDR 	(0x0844) 	/**< Interrupt Disable Register */
#define PIOC_IMR 	(0x0848) 	/**< Interrupt Mask Register */
#define PIOC_ISR 	(0x084C) 	/**< Interrupt Status Register */
#define PIOC_MDER 	(0x0850) 	/**< Multi-driver Enable Register */
#define PIOC_MDDR 	(0x0854) 	/**< Multi-driver Disable Register */
#define PIOC_MDSR 	(0x0858) 	/**< Multi-driver Status Register */
#define PIOC_PPUDR 	(0x0860) 	/**< Pull-up Disable Register */
#define PIOC_PPUER 	(0x0864) 	/**< Pull-up Enable Register */
#define PIOC_PPUSR 	(0x0868) 	/**< Pad Pull-up Status Register */
#define PIOC_ASR 	(0x0870) 	/**< Select A Register */
#define PIOC_BSR 	(0x0874) 	/**< Select B Register */
#define PIOC_ABSR 	(0x0878) 	/**< AB Select Status Register */
#define PIOC_OWER 	(0x08A0) 	/**< Output Write Enable Register */
#define PIOC_OWDR 	(0x08A4) 	/**< Output Write Disable Register */
#define PIOC_OWSR 	(0x08A8) 	/**< Output Write Status Register */
#define PIOD_PER 	(0x0A00) 	/**< PIO Enable Register */
#define PIOD_PDR 	(0x0A04) 	/**< PIO Disable Register */
#define PIOD_PSR 	(0x0A08) 	/**< PIO Status Register */
#define PIOD_OER 	(0x0A10) 	/**< Output Enable Register */
#define PIOD_ODR 	(0x0A14) 	/**< Output Disable Registerr */
#define PIOD_OSR 	(0x0A18) 	/**< Output Status Register */
#define PIOD_IFER 	(0x0A20) 	/**< Input Filter Enable Register */
#define PIOD_IFDR 	(0x0A24) 	/**< Input Filter Disable Register */
#define PIOD_IFSR 	(0x0A28) 	/**< Input Filter Status Register */
#define PIOD_SODR 	(0x0A30) 	/**< Set Output Data Register */
#define PIOD_CODR 	(0x0A34) 	/**< Clear Output Data Register */
#define PIOD_ODSR 	(0x0A38) 	/**< Output Data Status Register */
#define PIOD_PDSR 	(0x0A3C) 	/**< Pin Data Status Register */
#define PIOD_IER 	(0x0A40) 	/**< Interrupt Enable Register */
#define PIOD_IDR 	(0x0A44) 	/**< Interrupt Disable Register */
#define PIOD_IMR 	(0x0A48) 	/**< Interrupt Mask Register */
#define PIOD_ISR 	(0x0A4C) 	/**< Interrupt Status Register */
#define PIOD_MDER 	(0x0A50) 	/**< Multi-driver Enable Register */
#define PIOD_MDDR 	(0x0A54) 	/**< Multi-driver Disable Register */
#define PIOD_MDSR 	(0x0A58) 	/**< Multi-driver Status Register */
#define PIOD_PPUDR 	(0x0A60) 	/**< Pull-up Disable Register */
#define PIOD_PPUER 	(0x0A64) 	/**< Pull-up Enable Register */
#define PIOD_PPUSR 	(0x0A68) 	/**< Pad Pull-up Status Register */
#define PIOD_ASR 	(0x0A70) 	/**< Select A Register */
#define PIOD_BSR 	(0x0A74) 	/**< Select B Register */
#define PIOD_ABSR 	(0x0A78) 	/**< AB Select Status Register */
#define PIOD_OWER 	(0x0AA0) 	/**< Output Write Enable Register */
#define PIOD_OWDR 	(0x0AA4) 	/**< Output Write Disable Register */
#define PIOD_OWSR 	(0x0AA8) 	/**< Output Write Status Register */
#define PMC_SCER 	(0x0C00) 	/**< System Clock Enable Register */
#define PMC_SCDR 	(0x0C04) 	/**< System Clock Disable Register */
#define PMC_SCSR 	(0x0C08) 	/**< System Clock Status Register */
#define PMC_PCER 	(0x0C10) 	/**< Peripheral Clock Enable Register */
#define PMC_PCDR 	(0x0C14) 	/**< Peripheral Clock Disable Register */
#define PMC_PCSR 	(0x0C18) 	/**< Peripheral Clock Status Register */
#define CKGR_MOR 	(0x0C20) 	/**< Main Oscillator Register */
#define CKGR_MCFR 	(0x0C24) 	/**< Main Clock  Frequency Register */
#define CKGR_PLLAR 	(0x0C28) 	/**< PLL A Register */
#define CKGR_PLLBR 	(0x0C2C) 	/**< PLL B Register */
#define PMC_MCKR 	(0x0C30) 	/**< Master Clock Register */
#define PMC_PCKR 	(0x0C40) 	/**< Programmable Clock Register */
#define PMC_IER 	(0x0C60) 	/**< Interrupt Enable Register */
#define PMC_IDR 	(0x0C64) 	/**< Interrupt Disable Register */
#define PMC_SR 	(0x0C68) 	/**< Status Register */
#define PMC_IMR 	(0x0C6C) 	/**< Interrupt Mask Register */
#define ST_CR 	(0x0D00) 	/**< Control Register */
#define ST_PIMR 	(0x0D04) 	/**< Period Interval Mode Register */
#define ST_WDMR 	(0x0D08) 	/**< Watchdog Mode Register */
#define ST_RTMR 	(0x0D0C) 	/**< Real-time Mode Register */
#define ST_SR 	(0x0D10) 	/**< Status Register */
#define ST_IER 	(0x0D14) 	/**< Interrupt Enable Register */
#define ST_IDR 	(0x0D18) 	/**< Interrupt Disable Register */
#define ST_IMR 	(0x0D1C) 	/**< Interrupt Mask Register */
#define ST_RTAR 	(0x0D20) 	/**< Real-time Alarm Register */
#define ST_CRTR 	(0x0D24) 	/**< Current Real-time Register */
#define RTC_CR 	(0x0E00) 	/**< Control Register */
#define RTC_MR 	(0x0E04) 	/**< Mode Register */
#define RTC_TIMR 	(0x0E08) 	/**< Time Register */
#define RTC_CALR 	(0x0E0C) 	/**< Calendar Register */
#define RTC_TIMALR 	(0x0E10) 	/**< Time Alarm Register */
#define RTC_CALALR 	(0x0E14) 	/**< Calendar Alarm Register */
#define RTC_SR 	(0x0E18) 	/**< Status Register */
#define RTC_SCCR 	(0x0E1C) 	/**< Status Clear Command Register */
#define RTC_IER 	(0x0E20) 	/**< Interrupt Enable Register */
#define RTC_IDR 	(0x0E24) 	/**< Interrupt Disable Register */
#define RTC_IMR 	(0x0E28) 	/**< Interrupt Mask Register */
#define RTC_VER 	(0x0E2C) 	/**< Valid Entry Register */
#define MC_RCR 	(0x0F00) 	/**< MC Remap Control Register */
#define MC_ASR 	(0x0F04) 	/**< MC Abort Status Register */
#define MC_AASR 	(0x0F08) 	/**< MC Abort Address Status Register */
#define MC_PUIA 	(0x0F10) 	/**< MC Protection Unit Area */
#define MC_PUP 	(0x0F50) 	/**< MC Protection Unit Peripherals */
#define MC_PUER 	(0x0F54) 	/**< MC Protection Unit Enable Register */
#define EBI_CSA 	(0x0F60) 	/**< Chip Select Assignment Register */
#define EBI_CFGR 	(0x0F64) 	/**< Configuration Register */
#define EBI_SMC2_CSR 	(0x0F70) 	/**< SMC2 Chip Select Register */
#define EBI_SDRC_MR 	(0x0F90) 	/**< SDRAM Controller Mode Register */
#define EBI_SDRC_TR 	(0x0F94) 	/**< SDRAM Controller Refresh Timer Register */
#define EBI_SDRC_CR 	(0x0F98) 	/**< SDRAM Controller Configuration Register */
#define EBI_SDRC_SRR 	(0x0F9C) 	/**< SDRAM Controller Self Refresh Register */
#define EBI_SDRC_LPR 	(0x0FA0) 	/**< SDRAM Controller Low Power Register */
#define EBI_SDRC_IER 	(0x0FA4) 	/**< SDRAM Controller Interrupt Enable Register */
#define EBI_SDRC_IDR 	(0x0FA8) 	/**< SDRAM Controller Interrupt Disable Register */
#define EBI_SDRC_IMR 	(0x0FAC) 	/**< SDRAM Controller Interrupt Mask Register */
#define EBI_SDRC_ISR 	(0x0FB0) 	/**< SDRAM Controller Interrupt Mask Register */
#define EBI_BFC_MR 	(0x0FC0) 	/**< BFC Mode Register */

/* -------------------------------------------------------- */
/* Bitfields definition for SYS hardware peripheral */
/* -------------------------------------------------------- */

#endif /* __AT91RM9200_SYS_H */