📄 at91rm9200_mci.h
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/* linux/include/asm-arm/arch-at91rm9200/at91rm9200_mci.h
*
* Hardware definition for the mci peripheral in the ATMEL at91rm9200 processor
*
* Generated 01/09/2006 (16:49:36) AT91 SW Application Group from MCI_1764A V1.4
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __AT91RM9200_MCI_H
#define __AT91RM9200_MCI_H
/* -------------------------------------------------------- */
/* MCI ID definitions for AT91RM9200 */
/* -------------------------------------------------------- */
#ifndef AT91C_ID_MCI
#define AT91C_ID_MCI 10 /**< Multimedia Card Interface id */
#endif /* AT91C_ID_MCI */
/* -------------------------------------------------------- */
/* MCI Base Address definitions for AT91RM9200 */
/* -------------------------------------------------------- */
#define AT91C_BASE_MCI 0xFFFB4000 /**< MCI base address */
/* -------------------------------------------------------- */
/* PIO definition for MCI hardware peripheral */
/* -------------------------------------------------------- */
#define AT91C_PA28_MCCDA (1 << 28) /**< Multimedia Card A Command */
#define AT91C_PA27_MCCK (1 << 27) /**< Multimedia Card Clock */
#define AT91C_PA29_MCDA0 (1 << 29) /**< Multimedia Card A Data 0 */
#define AT91C_PB3_MCDA1 (1 << 3) /**< Multimedia Card A Data 1 */
#define AT91C_PB4_MCDA2 (1 << 4) /**< Multimedia Card A Data 2 */
#define AT91C_PB5_MCDA3 (1 << 5) /**< Multimedia Card A Data 3 */
/* -------------------------------------------------------- */
/* Register offset definition for MCI hardware peripheral */
/* -------------------------------------------------------- */
#define MCI_CR (0x0000) /**< MCI Control Register */
#define MCI_MR (0x0004) /**< MCI Mode Register */
#define MCI_DTOR (0x0008) /**< MCI Data Timeout Register */
#define MCI_SDCR (0x000C) /**< MCI SD Card Register */
#define MCI_ARGR (0x0010) /**< MCI Argument Register */
#define MCI_CMDR (0x0014) /**< MCI Command Register */
#define MCI_RSPR (0x0020) /**< MCI Response Register */
#define MCI_RDR (0x0030) /**< MCI Receive Data Register */
#define MCI_TDR (0x0034) /**< MCI Transmit Data Register */
#define MCI_SR (0x0040) /**< MCI Status Register */
#define MCI_IER (0x0044) /**< MCI Interrupt Enable Register */
#define MCI_IDR (0x0048) /**< MCI Interrupt Disable Register */
#define MCI_IMR (0x004C) /**< MCI Interrupt Mask Register */
#define MCI_RPR (0x0100) /**< Receive Pointer Register */
#define MCI_RCR (0x0104) /**< Receive Counter Register */
#define MCI_TPR (0x0108) /**< Transmit Pointer Register */
#define MCI_TCR (0x010C) /**< Transmit Counter Register */
#define MCI_RNPR (0x0110) /**< Receive Next Pointer Register */
#define MCI_RNCR (0x0114) /**< Receive Next Counter Register */
#define MCI_TNPR (0x0118) /**< Transmit Next Pointer Register */
#define MCI_TNCR (0x011C) /**< Transmit Next Counter Register */
#define MCI_PTCR (0x0120) /**< PDC Transfer Control Register */
#define MCI_PTSR (0x0124) /**< PDC Transfer Status Register */
/* -------------------------------------------------------- */
/* Bitfields definition for MCI hardware peripheral */
/* -------------------------------------------------------- */
/* --- Register MCI_CR */
#define AT91C_MCI_MCIEN (0x1 << 0 ) /**< (MCI) Multimedia Interface Enable */
#define AT91C_MCI_MCIDIS (0x1 << 1 ) /**< (MCI) Multimedia Interface Disable */
#define AT91C_MCI_PWSEN (0x1 << 2 ) /**< (MCI) Power Save Mode Enable */
#define AT91C_MCI_PWSDIS (0x1 << 3 ) /**< (MCI) Power Save Mode Disable */
#define AT91C_MCI_SWRST (0x1 << 7 ) /**< (MCI) MCI Software reset */
/* --- Register MCI_MR */
#define AT91C_MCI_CLKDIV (0xFF << 0 ) /**< (MCI) Clock Divider */
#define AT91C_MCI_PWSDIV (0x7 << 8 ) /**< (MCI) Power Saving Divider */
#define AT91C_MCI_PDCPADV (0x1 << 14) /**< (MCI) PDC Padding Value */
#define AT91C_MCI_PDCMODE (0x1 << 15) /**< (MCI) PDC Oriented Mode */
#define AT91C_MCI_BLKLEN (0xFFF << 18) /**< (MCI) Data Block Length */
/* --- Register MCI_DTOR */
#define AT91C_MCI_DTOCYC (0xF << 0 ) /**< (MCI) Data Timeout Cycle Number */
#define AT91C_MCI_DTOMUL (0x7 << 4 ) /**< (MCI) Data Timeout Multiplier */
#define AT91C_MCI_DTOMUL_1 (0x0 << 4) /**< (MCI) DTOCYC x 1 */
#define AT91C_MCI_DTOMUL_16 (0x1 << 4) /**< (MCI) DTOCYC x 16 */
#define AT91C_MCI_DTOMUL_128 (0x2 << 4) /**< (MCI) DTOCYC x 128 */
#define AT91C_MCI_DTOMUL_256 (0x3 << 4) /**< (MCI) DTOCYC x 256 */
#define AT91C_MCI_DTOMUL_1024 (0x4 << 4) /**< (MCI) DTOCYC x 1024 */
#define AT91C_MCI_DTOMUL_4096 (0x5 << 4) /**< (MCI) DTOCYC x 4096 */
#define AT91C_MCI_DTOMUL_65536 (0x6 << 4) /**< (MCI) DTOCYC x 65536 */
#define AT91C_MCI_DTOMUL_1048576 (0x7 << 4) /**< (MCI) DTOCYC x 1048576 */
/* --- Register MCI_SDCR */
#define AT91C_MCI_SCDSEL (0xF << 0 ) /**< (MCI) SD Card Selector */
#define AT91C_MCI_SCDBUS (0x1 << 7 ) /**< (MCI) SD Card Bus Width */
/* --- Register MCI_CMDR */
#define AT91C_MCI_CMDNB (0x3F << 0 ) /**< (MCI) Command Number */
#define AT91C_MCI_RSPTYP (0x3 << 6 ) /**< (MCI) Response Type */
#define AT91C_MCI_RSPTYP_NO (0x0 << 6) /**< (MCI) No response */
#define AT91C_MCI_RSPTYP_48 (0x1 << 6) /**< (MCI) 48-bit response */
#define AT91C_MCI_RSPTYP_136 (0x2 << 6) /**< (MCI) 136-bit response */
#define AT91C_MCI_SPCMD (0x7 << 8 ) /**< (MCI) Special CMD */
#define AT91C_MCI_SPCMD_NONE (0x0 << 8) /**< (MCI) Not a special CMD */
#define AT91C_MCI_SPCMD_INIT (0x1 << 8) /**< (MCI) Initialization CMD */
#define AT91C_MCI_SPCMD_SYNC (0x2 << 8) /**< (MCI) Synchronized CMD */
#define AT91C_MCI_SPCMD_IT_CMD (0x4 << 8) /**< (MCI) Interrupt command */
#define AT91C_MCI_SPCMD_IT_REP (0x5 << 8) /**< (MCI) Interrupt response */
#define AT91C_MCI_OPDCMD (0x1 << 11) /**< (MCI) Open Drain Command */
#define AT91C_MCI_MAXLAT (0x1 << 12) /**< (MCI) Maximum Latency for Command to respond */
#define AT91C_MCI_TRCMD (0x3 << 16) /**< (MCI) Transfer CMD */
#define AT91C_MCI_TRCMD_NO (0x0 << 16) /**< (MCI) No transfer */
#define AT91C_MCI_TRCMD_START (0x1 << 16) /**< (MCI) Start transfer */
#define AT91C_MCI_TRCMD_STOP (0x2 << 16) /**< (MCI) Stop transfer */
#define AT91C_MCI_TRDIR (0x1 << 18) /**< (MCI) Transfer Direction */
#define AT91C_MCI_TRTYP (0x3 << 19) /**< (MCI) Transfer Type */
#define AT91C_MCI_TRTYP_BLOCK (0x0 << 19) /**< (MCI) Block Transfer type */
#define AT91C_MCI_TRTYP_MULTIPLE (0x1 << 19) /**< (MCI) Multiple Block transfer type */
#define AT91C_MCI_TRTYP_STREAM (0x2 << 19) /**< (MCI) Stream transfer type */
/* --- Register MCI_SR */
#define AT91C_MCI_CMDRDY (0x1 << 0 ) /**< (MCI) Command Ready flag */
#define AT91C_MCI_RXRDY (0x1 << 1 ) /**< (MCI) RX Ready flag */
#define AT91C_MCI_TXRDY (0x1 << 2 ) /**< (MCI) TX Ready flag */
#define AT91C_MCI_BLKE (0x1 << 3 ) /**< (MCI) Data Block Transfer Ended flag */
#define AT91C_MCI_DTIP (0x1 << 4 ) /**< (MCI) Data Transfer in Progress flag */
#define AT91C_MCI_NOTBUSY (0x1 << 5 ) /**< (MCI) Data Line Not Busy flag */
#define AT91C_MCI_ENDRX (0x1 << 6 ) /**< (MCI) End of RX Buffer flag */
#define AT91C_MCI_ENDTX (0x1 << 7 ) /**< (MCI) End of TX Buffer flag */
#define AT91C_MCI_RXBUFF (0x1 << 14) /**< (MCI) RX Buffer Full flag */
#define AT91C_MCI_TXBUFE (0x1 << 15) /**< (MCI) TX Buffer Empty flag */
#define AT91C_MCI_RINDE (0x1 << 16) /**< (MCI) Response Index Error flag */
#define AT91C_MCI_RDIRE (0x1 << 17) /**< (MCI) Response Direction Error flag */
#define AT91C_MCI_RCRCE (0x1 << 18) /**< (MCI) Response CRC Error flag */
#define AT91C_MCI_RENDE (0x1 << 19) /**< (MCI) Response End Bit Error flag */
#define AT91C_MCI_RTOE (0x1 << 20) /**< (MCI) Response Time-out Error flag */
#define AT91C_MCI_DCRCE (0x1 << 21) /**< (MCI) data CRC Error flag */
#define AT91C_MCI_DTOE (0x1 << 22) /**< (MCI) Data timeout Error flag */
#define AT91C_MCI_OVRE (0x1 << 30) /**< (MCI) Overrun flag */
#define AT91C_MCI_UNRE (0x1 << 31) /**< (MCI) Underrun flag */
/* --- Register MCI_IER */
#define AT91C_MCI_CMDRDY (0x1 << 0 ) /**< (MCI) Command Ready flag */
#define AT91C_MCI_RXRDY (0x1 << 1 ) /**< (MCI) RX Ready flag */
#define AT91C_MCI_TXRDY (0x1 << 2 ) /**< (MCI) TX Ready flag */
#define AT91C_MCI_BLKE (0x1 << 3 ) /**< (MCI) Data Block Transfer Ended flag */
#define AT91C_MCI_DTIP (0x1 << 4 ) /**< (MCI) Data Transfer in Progress flag */
#define AT91C_MCI_NOTBUSY (0x1 << 5 ) /**< (MCI) Data Line Not Busy flag */
#define AT91C_MCI_ENDRX (0x1 << 6 ) /**< (MCI) End of RX Buffer flag */
#define AT91C_MCI_ENDTX (0x1 << 7 ) /**< (MCI) End of TX Buffer flag */
#define AT91C_MCI_RXBUFF (0x1 << 14) /**< (MCI) RX Buffer Full flag */
#define AT91C_MCI_TXBUFE (0x1 << 15) /**< (MCI) TX Buffer Empty flag */
#define AT91C_MCI_RINDE (0x1 << 16) /**< (MCI) Response Index Error flag */
#define AT91C_MCI_RDIRE (0x1 << 17) /**< (MCI) Response Direction Error flag */
#define AT91C_MCI_RCRCE (0x1 << 18) /**< (MCI) Response CRC Error flag */
#define AT91C_MCI_RENDE (0x1 << 19) /**< (MCI) Response End Bit Error flag */
#define AT91C_MCI_RTOE (0x1 << 20) /**< (MCI) Response Time-out Error flag */
#define AT91C_MCI_DCRCE (0x1 << 21) /**< (MCI) data CRC Error flag */
#define AT91C_MCI_DTOE (0x1 << 22) /**< (MCI) Data timeout Error flag */
#define AT91C_MCI_OVRE (0x1 << 30) /**< (MCI) Overrun flag */
#define AT91C_MCI_UNRE (0x1 << 31) /**< (MCI) Underrun flag */
/* --- Register MCI_IDR */
#define AT91C_MCI_CMDRDY (0x1 << 0 ) /**< (MCI) Command Ready flag */
#define AT91C_MCI_RXRDY (0x1 << 1 ) /**< (MCI) RX Ready flag */
#define AT91C_MCI_TXRDY (0x1 << 2 ) /**< (MCI) TX Ready flag */
#define AT91C_MCI_BLKE (0x1 << 3 ) /**< (MCI) Data Block Transfer Ended flag */
#define AT91C_MCI_DTIP (0x1 << 4 ) /**< (MCI) Data Transfer in Progress flag */
#define AT91C_MCI_NOTBUSY (0x1 << 5 ) /**< (MCI) Data Line Not Busy flag */
#define AT91C_MCI_ENDRX (0x1 << 6 ) /**< (MCI) End of RX Buffer flag */
#define AT91C_MCI_ENDTX (0x1 << 7 ) /**< (MCI) End of TX Buffer flag */
#define AT91C_MCI_RXBUFF (0x1 << 14) /**< (MCI) RX Buffer Full flag */
#define AT91C_MCI_TXBUFE (0x1 << 15) /**< (MCI) TX Buffer Empty flag */
#define AT91C_MCI_RINDE (0x1 << 16) /**< (MCI) Response Index Error flag */
#define AT91C_MCI_RDIRE (0x1 << 17) /**< (MCI) Response Direction Error flag */
#define AT91C_MCI_RCRCE (0x1 << 18) /**< (MCI) Response CRC Error flag */
#define AT91C_MCI_RENDE (0x1 << 19) /**< (MCI) Response End Bit Error flag */
#define AT91C_MCI_RTOE (0x1 << 20) /**< (MCI) Response Time-out Error flag */
#define AT91C_MCI_DCRCE (0x1 << 21) /**< (MCI) data CRC Error flag */
#define AT91C_MCI_DTOE (0x1 << 22) /**< (MCI) Data timeout Error flag */
#define AT91C_MCI_OVRE (0x1 << 30) /**< (MCI) Overrun flag */
#define AT91C_MCI_UNRE (0x1 << 31) /**< (MCI) Underrun flag */
/* --- Register MCI_IMR */
#define AT91C_MCI_CMDRDY (0x1 << 0 ) /**< (MCI) Command Ready flag */
#define AT91C_MCI_RXRDY (0x1 << 1 ) /**< (MCI) RX Ready flag */
#define AT91C_MCI_TXRDY (0x1 << 2 ) /**< (MCI) TX Ready flag */
#define AT91C_MCI_BLKE (0x1 << 3 ) /**< (MCI) Data Block Transfer Ended flag */
#define AT91C_MCI_DTIP (0x1 << 4 ) /**< (MCI) Data Transfer in Progress flag */
#define AT91C_MCI_NOTBUSY (0x1 << 5 ) /**< (MCI) Data Line Not Busy flag */
#define AT91C_MCI_ENDRX (0x1 << 6 ) /**< (MCI) End of RX Buffer flag */
#define AT91C_MCI_ENDTX (0x1 << 7 ) /**< (MCI) End of TX Buffer flag */
#define AT91C_MCI_RXBUFF (0x1 << 14) /**< (MCI) RX Buffer Full flag */
#define AT91C_MCI_TXBUFE (0x1 << 15) /**< (MCI) TX Buffer Empty flag */
#define AT91C_MCI_RINDE (0x1 << 16) /**< (MCI) Response Index Error flag */
#define AT91C_MCI_RDIRE (0x1 << 17) /**< (MCI) Response Direction Error flag */
#define AT91C_MCI_RCRCE (0x1 << 18) /**< (MCI) Response CRC Error flag */
#define AT91C_MCI_RENDE (0x1 << 19) /**< (MCI) Response End Bit Error flag */
#define AT91C_MCI_RTOE (0x1 << 20) /**< (MCI) Response Time-out Error flag */
#define AT91C_MCI_DCRCE (0x1 << 21) /**< (MCI) data CRC Error flag */
#define AT91C_MCI_DTOE (0x1 << 22) /**< (MCI) Data timeout Error flag */
#define AT91C_MCI_OVRE (0x1 << 30) /**< (MCI) Overrun flag */
#define AT91C_MCI_UNRE (0x1 << 31) /**< (MCI) Underrun flag */
#endif /* __AT91RM9200_MCI_H */
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