at91rm9200_sdrc.h

arch-at91rm9200

/* linux/include/asm-arm/arch-at91rm9200/at91rm9200_sdrc.h
 * 
 * Hardware definition for the sdrc peripheral in the ATMEL at91rm9200 processor
 * 
 * Generated  01/09/2006 (16:49:36) AT91 SW Application Group from SDRC_1758B V1.2
 * 
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 * 
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * You should have received a copy of the  GNU General Public License along
 * with this program; if not, write  to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */


#ifndef __AT91RM9200_SDRC_H
#define __AT91RM9200_SDRC_H

/* -------------------------------------------------------- */
/* SDRC ID definitions for  AT91RM9200           */
/* -------------------------------------------------------- */

/* -------------------------------------------------------- */
/* SDRC Base Address definitions for  AT91RM9200   */
/* -------------------------------------------------------- */
#define AT91C_BASE_SDRC      	0xFFFFFF90 /**< SDRC base address */

/* -------------------------------------------------------- */
/* PIO definition for SDRC hardware peripheral */
/* -------------------------------------------------------- */
#define AT91C_PC16_D16      	(1 << 16) /**< Data Bus [16] */
#define AT91C_PC17_D17      	(1 << 17) /**< Data Bus [17] */
#define AT91C_PC18_D18      	(1 << 18) /**< Data Bus [18] */
#define AT91C_PC19_D19      	(1 << 19) /**< Data Bus [19] */
#define AT91C_PC20_D20      	(1 << 20) /**< Data Bus [20] */
#define AT91C_PC21_D21      	(1 << 21) /**< Data Bus [21] */
#define AT91C_PC22_D22      	(1 << 22) /**< Data Bus [22] */
#define AT91C_PC23_D23      	(1 << 23) /**< Data Bus [23] */
#define AT91C_PC24_D24      	(1 << 24) /**< Data Bus [24] */
#define AT91C_PC25_D25      	(1 << 25) /**< Data Bus [25] */
#define AT91C_PC26_D26      	(1 << 26) /**< Data Bus [26] */
#define AT91C_PC27_D27      	(1 << 27) /**< Data Bus [27] */
#define AT91C_PC28_D28      	(1 << 28) /**< Data Bus [28] */
#define AT91C_PC29_D29      	(1 << 29) /**< Data Bus [29] */
#define AT91C_PC30_D30      	(1 << 30) /**< Data Bus [30] */
#define AT91C_PC31_D31      	(1 << 31) /**< Data Bus [31] */


/* -------------------------------------------------------- */
/* Register offset definition for SDRC hardware peripheral */
/* -------------------------------------------------------- */
#define SDRC_MR 	(0x0000) 	/**< SDRAM Controller Mode Register */
#define SDRC_TR 	(0x0004) 	/**< SDRAM Controller Refresh Timer Register */
#define SDRC_CR 	(0x0008) 	/**< SDRAM Controller Configuration Register */
#define SDRC_SRR 	(0x000C) 	/**< SDRAM Controller Self Refresh Register */
#define SDRC_LPR 	(0x0010) 	/**< SDRAM Controller Low Power Register */
#define SDRC_IER 	(0x0014) 	/**< SDRAM Controller Interrupt Enable Register */
#define SDRC_IDR 	(0x0018) 	/**< SDRAM Controller Interrupt Disable Register */
#define SDRC_IMR 	(0x001C) 	/**< SDRAM Controller Interrupt Mask Register */
#define SDRC_ISR 	(0x0020) 	/**< SDRAM Controller Interrupt Mask Register */

/* -------------------------------------------------------- */
/* Bitfields definition for SDRC hardware peripheral */
/* -------------------------------------------------------- */
/* --- Register SDRC_MR */
#define AT91C_SDRC_MODE       (0xF << 0 ) /**< (SDRC) Mode */
#define 	AT91C_SDRC_MODE_NORMAL_CMD           0x0 /**< (SDRC) Normal Mode */
#define 	AT91C_SDRC_MODE_NOP_CMD              0x1 /**< (SDRC) NOP Command */
#define 	AT91C_SDRC_MODE_PRCGALL_CMD          0x2 /**< (SDRC) All Banks Precharge Command */
#define 	AT91C_SDRC_MODE_LMR_CMD              0x3 /**< (SDRC) Load Mode Register Command */
#define 	AT91C_SDRC_MODE_RFSH_CMD             0x4 /**< (SDRC) Refresh Command */
#define AT91C_SDRC_DBW        (0x1 << 4 ) /**< (SDRC) Data Bus Width */
#define 	AT91C_SDRC_DBW_32_BITS              (0x0 <<  4) /**< (SDRC) 32 Bits datas bus */
#define 	AT91C_SDRC_DBW_16_BITS              (0x1 <<  4) /**< (SDRC) 16 Bits datas bus */
/* --- Register SDRC_TR */
#define AT91C_SDRC_COUNT      (0xFFF << 0 ) /**< (SDRC) Refresh Counter */
/* --- Register SDRC_CR */
#define AT91C_SDRC_NC         (0x3 << 0 ) /**< (SDRC) Number of Column Bits */
#define 	AT91C_SDRC_NC_8                    0x0 /**< (SDRC) 8 Bits */
#define 	AT91C_SDRC_NC_9                    0x1 /**< (SDRC) 9 Bits */
#define 	AT91C_SDRC_NC_10                   0x2 /**< (SDRC) 10 Bits */
#define 	AT91C_SDRC_NC_11                   0x3 /**< (SDRC) 11 Bits */
#define AT91C_SDRC_NR         (0x3 << 2 ) /**< (SDRC) Number of Row Bits */
#define 	AT91C_SDRC_NR_11                   (0x0 <<  2) /**< (SDRC) 11 Bits */
#define 	AT91C_SDRC_NR_12                   (0x1 <<  2) /**< (SDRC) 12 Bits */
#define 	AT91C_SDRC_NR_13                   (0x2 <<  2) /**< (SDRC) 13 Bits */
#define AT91C_SDRC_NB         (0x1 << 4 ) /**< (SDRC) Number of Banks */
#define 	AT91C_SDRC_NB_2_BANKS              (0x0 <<  4) /**< (SDRC) 2 banks */
#define 	AT91C_SDRC_NB_4_BANKS              (0x1 <<  4) /**< (SDRC) 4 banks */
#define AT91C_SDRC_CAS        (0x3 << 5 ) /**< (SDRC) CAS Latency */
#define 	AT91C_SDRC_CAS_2                    (0x2 <<  5) /**< (SDRC) 2 cycles */
#define AT91C_SDRC_TWR        (0xF << 7 ) /**< (SDRC) Number of Write Recovery Time Cycles */
#define AT91C_SDRC_TRC        (0xF << 11) /**< (SDRC) Number of RAS Cycle Time Cycles */
#define AT91C_SDRC_TRP        (0xF << 15) /**< (SDRC) Number of RAS Precharge Time Cycles */
#define AT91C_SDRC_TRCD       (0xF << 19) /**< (SDRC) Number of RAS to CAS Delay Cycles */
#define AT91C_SDRC_TRAS       (0xF << 23) /**< (SDRC) Number of RAS Active Time Cycles */
#define AT91C_SDRC_TXSR       (0xF << 27) /**< (SDRC) Number of Command Recovery Time Cycles */
/* --- Register SDRC_SRR */
#define AT91C_SDRC_SRCB       (0x1 << 0 ) /**< (SDRC) Self-refresh Command Bit */
/* --- Register SDRC_LPR */
#define AT91C_SDRC_LPCB       (0x1 << 0 ) /**< (SDRC) Low-power Command Bit */
/* --- Register SDRC_IER */
#define AT91C_SDRC_RES        (0x1 << 0 ) /**< (SDRC) Refresh Error Status */
/* --- Register SDRC_IDR */
#define AT91C_SDRC_RES        (0x1 << 0 ) /**< (SDRC) Refresh Error Status */
/* --- Register SDRC_IMR */
#define AT91C_SDRC_RES        (0x1 << 0 ) /**< (SDRC) Refresh Error Status */
/* --- Register SDRC_ISR */
#define AT91C_SDRC_RES        (0x1 << 0 ) /**< (SDRC) Refresh Error Status */

#endif /* __AT91RM9200_SDRC_H */