at91rm9200.grd

AT91RM9200-BasicTools-IAR4_30A-1_2

# ========== Register definition for PDC_SSC1 peripheral ========== 
    AT91C_SSC2_RHR {desc="Receive Holding Register";
        hk="Receive Holding Register";
        access="memorymapped"; address=0xFFFD8020}
    AT91C_SSC1_PTCR {desc="PDC Transfer Control Register";
        hk="PDC Transfer Control Register";
        access="memorymapped"; address=0xFFFD4120}
    AT91C_SSC1_TNPR {desc="Transmit Next Pointer Register";
        hk="Transmit Next Pointer Register";
        access="memorymapped"; address=0xFFFD4118}
    AT91C_SSC1_RNPR {desc="Receive Next Pointer Register";
        hk="Receive Next Pointer Register";
        access="memorymapped"; address=0xFFFD4110}
    AT91C_SSC1_TPR {desc="Transmit Pointer Register";
        hk="Transmit Pointer Register";
        access="memorymapped"; address=0xFFFD4108}
    AT91C_SSC1_RPR {desc="Receive Pointer Register";
        hk="Receive Pointer Register";
        access="memorymapped"; address=0xFFFD4100}
    AT91C_SSC1_PTSR {desc="PDC Transfer Status Register";
        hk="PDC Transfer Status Register";
        access="memorymapped"; address=0xFFFD4124}
    AT91C_SSC1_TNCR {desc="Transmit Next Counter Register";
        hk="Transmit Next Counter Register";
        access="memorymapped"; address=0xFFFD411C}
    AT91C_SSC1_RNCR {desc="Receive Next Counter Register";
        hk="Receive Next Counter Register";
        access="memorymapped"; address=0xFFFD4114}
    AT91C_SSC1_TCR {desc="Transmit Counter Register";
        hk="Transmit Counter Register";
        access="memorymapped"; address=0xFFFD410C}
# ========== Register definition for SSC1 peripheral ========== 
    AT91C_SSC1_RCR {desc="Receive Counter Register";
        hk="Receive Counter Register";
        access="memorymapped"; address=0xFFFD4104}
    AT91C_SSC1_RFMR {desc="Receive Frame Mode Register";
        hk="Receive Frame Mode Register";
        access="memorymapped"; address=0xFFFD4014}
    AT91C_SSC1_CMR {desc="Clock Mode Register";
        hk="Clock Mode Register";
        access="memorymapped"; address=0xFFFD4004}
    AT91C_SSC1_IDR {desc="Interrupt Disable Register";
        hk="Interrupt Disable Register";
        access="memorymapped"; address=0xFFFD4048}
    AT91C_SSC1_SR {desc="Status Register";
        hk="Status Register";
        access="memorymapped"; address=0xFFFD4040}
    AT91C_SSC1_RC0R {desc="Receive Compare 0 Register";
        hk="Receive Compare 0 Register";
        access="memorymapped"; address=0xFFFD4038}
    AT91C_SSC1_RSHR {desc="Receive Sync Holding Register";
        hk="Receive Sync Holding Register";
        access="memorymapped"; address=0xFFFD4030}
    AT91C_SSC1_RHR {desc="Receive Holding Register";
        hk="Receive Holding Register";
        access="memorymapped"; address=0xFFFD4020}
    AT91C_SSC1_TCMR {desc="Transmit Clock Mode Register";
        hk="Transmit Clock Mode Register";
        access="memorymapped"; address=0xFFFD4018}
    AT91C_SSC1_RCMR {desc="Receive Clock ModeRegister";
        hk="Receive Clock ModeRegister";
        access="memorymapped"; address=0xFFFD4010}
    AT91C_SSC1_CR {desc="Control Register";
        hk="Control Register";
        access="memorymapped"; address=0xFFFD4000}
    AT91C_SSC1_IMR {desc="Interrupt Mask Register";
        hk="Interrupt Mask Register";
        access="memorymapped"; address=0xFFFD404C}
    AT91C_SSC1_IER {desc="Interrupt Enable Register";
        hk="Interrupt Enable Register";
        access="memorymapped"; address=0xFFFD4044}
    AT91C_SSC1_RC1R {desc="Receive Compare 1 Register";
        hk="Receive Compare 1 Register";
        access="memorymapped"; address=0xFFFD403C}
    AT91C_SSC1_TSHR {desc="Transmit Sync Holding Register";
        hk="Transmit Sync Holding Register";
        access="memorymapped"; address=0xFFFD4034}
    AT91C_SSC1_THR {desc="Transmit Holding Register";
        hk="Transmit Holding Register";
        access="memorymapped"; address=0xFFFD4024}
# ========== Register definition for PDC_SSC0 peripheral ========== 
    AT91C_SSC1_TFMR {desc="Transmit Frame Mode Register";
        hk="Transmit Frame Mode Register";
        access="memorymapped"; address=0xFFFD401C}
    AT91C_SSC0_PTCR {desc="PDC Transfer Control Register";
        hk="PDC Transfer Control Register";
        access="memorymapped"; address=0xFFFD0120}
    AT91C_SSC0_TNPR {desc="Transmit Next Pointer Register";
        hk="Transmit Next Pointer Register";
        access="memorymapped"; address=0xFFFD0118}
    AT91C_SSC0_RNPR {desc="Receive Next Pointer Register";
        hk="Receive Next Pointer Register";
        access="memorymapped"; address=0xFFFD0110}
    AT91C_SSC0_TPR {desc="Transmit Pointer Register";
        hk="Transmit Pointer Register";
        access="memorymapped"; address=0xFFFD0108}
    AT91C_SSC0_RPR {desc="Receive Pointer Register";
        hk="Receive Pointer Register";
        access="memorymapped"; address=0xFFFD0100}
    AT91C_SSC0_PTSR {desc="PDC Transfer Status Register";
        hk="PDC Transfer Status Register";
        access="memorymapped"; address=0xFFFD0124}
    AT91C_SSC0_TNCR {desc="Transmit Next Counter Register";
        hk="Transmit Next Counter Register";
        access="memorymapped"; address=0xFFFD011C}
    AT91C_SSC0_RNCR {desc="Receive Next Counter Register";
        hk="Receive Next Counter Register";
        access="memorymapped"; address=0xFFFD0114}
    AT91C_SSC0_TCR {desc="Transmit Counter Register";
        hk="Transmit Counter Register";
        access="memorymapped"; address=0xFFFD010C}
# ========== Register definition for SSC0 peripheral ========== 
    AT91C_SSC0_RCR {desc="Receive Counter Register";
        hk="Receive Counter Register";
        access="memorymapped"; address=0xFFFD0104}
    AT91C_SSC0_IMR {desc="Interrupt Mask Register";
        hk="Interrupt Mask Register";
        access="memorymapped"; address=0xFFFD004C}
    AT91C_SSC0_IER {desc="Interrupt Enable Register";
        hk="Interrupt Enable Register";
        access="memorymapped"; address=0xFFFD0044}
    AT91C_SSC0_RC1R {desc="Receive Compare 1 Register";
        hk="Receive Compare 1 Register";
        access="memorymapped"; address=0xFFFD003C}
    AT91C_SSC0_TSHR {desc="Transmit Sync Holding Register";
        hk="Transmit Sync Holding Register";
        access="memorymapped"; address=0xFFFD0034}
    AT91C_SSC0_THR {desc="Transmit Holding Register";
        hk="Transmit Holding Register";
        access="memorymapped"; address=0xFFFD0024}
    AT91C_SSC0_TFMR {desc="Transmit Frame Mode Register";
        hk="Transmit Frame Mode Register";
        access="memorymapped"; address=0xFFFD001C}
    AT91C_SSC0_RFMR {desc="Receive Frame Mode Register";
        hk="Receive Frame Mode Register";
        access="memorymapped"; address=0xFFFD0014}
    AT91C_SSC0_CMR {desc="Clock Mode Register";
        hk="Clock Mode Register";
        access="memorymapped"; address=0xFFFD0004}
    AT91C_SSC0_IDR {desc="Interrupt Disable Register";
        hk="Interrupt Disable Register";
        access="memorymapped"; address=0xFFFD0048}
    AT91C_SSC0_SR {desc="Status Register";
        hk="Status Register";
        access="memorymapped"; address=0xFFFD0040}
    AT91C_SSC0_RC0R {desc="Receive Compare 0 Register";
        hk="Receive Compare 0 Register";
        access="memorymapped"; address=0xFFFD0038}
    AT91C_SSC0_RSHR {desc="Receive Sync Holding Register";
        hk="Receive Sync Holding Register";
        access="memorymapped"; address=0xFFFD0030}
    AT91C_SSC0_RHR {desc="Receive Holding Register";
        hk="Receive Holding Register";
        access="memorymapped"; address=0xFFFD0020}
    AT91C_SSC0_TCMR {desc="Transmit Clock Mode Register";
        hk="Transmit Clock Mode Register";
        access="memorymapped"; address=0xFFFD0018}
    AT91C_SSC0_RCMR {desc="Receive Clock ModeRegister";
        hk="Receive Clock ModeRegister";
        access="memorymapped"; address=0xFFFD0010}
# ========== Register definition for PDC_US3 peripheral ========== 
    AT91C_SSC0_CR {desc="Control Register";
        hk="Control Register";
        access="memorymapped"; address=0xFFFD0000}
    AT91C_US3_PTSR {desc="PDC Transfer Status Register";
        hk="PDC Transfer Status Register";
        access="memorymapped"; address=0xFFFCC124}
    AT91C_US3_TNCR {desc="Transmit Next Counter Register";
        hk="Transmit Next Counter Register";
        access="memorymapped"; address=0xFFFCC11C}
    AT91C_US3_RNCR {desc="Receive Next Counter Register";
        hk="Receive Next Counter Register";
        access="memorymapped"; address=0xFFFCC114}
    AT91C_US3_TCR {desc="Transmit Counter Register";
        hk="Transmit Counter Register";
        access="memorymapped"; address=0xFFFCC10C}
    AT91C_US3_RCR {desc="Receive Counter Register";
        hk="Receive Counter Register";
        access="memorymapped"; address=0xFFFCC104}
    AT91C_US3_PTCR {desc="PDC Transfer Control Register";
        hk="PDC Transfer Control Register";
        access="memorymapped"; address=0xFFFCC120}
    AT91C_US3_TNPR {desc="Transmit Next Pointer Register";
        hk="Transmit Next Pointer Register";
        access="memorymapped"; address=0xFFFCC118}
    AT91C_US3_RNPR {desc="Receive Next Pointer Register";
        hk="Receive Next Pointer Register";
        access="memorymapped"; address=0xFFFCC110}
    AT91C_US3_TPR {desc="Transmit Pointer Register";
        hk="Transmit Pointer Register";
        access="memorymapped"; address=0xFFFCC108}
# ========== Register definition for US3 peripheral ========== 
    AT91C_US3_RPR {desc="Receive Pointer Register";
        hk="Receive Pointer Register";
        access="memorymapped"; address=0xFFFCC100}
    AT91C_US3_IF {desc="IRDA_FILTER Register";
        hk="IRDA_FILTER Register";
        access="memorymapped"; address=0xFFFCC04C}
    AT91C_US3_NER {desc="Nb Errors Register";
        hk="Nb Errors Register";
        access="memorymapped"; address=0xFFFCC044}
    AT91C_US3_RTOR {desc="Receiver Time-out Register";
        hk="Receiver Time-out Register";
        access="memorymapped"; address=0xFFFCC024}
    AT91C_US3_THR {desc="Transmitter Holding Register";
        hk="Transmitter Holding Register";
        access="memorymapped"; address=0xFFFCC01C}
    AT91C_US3_CSR {desc="Channel Status Register";
        hk="Channel Status Register";
        access="memorymapped"; address=0xFFFCC014}
    AT91C_US3_IDR {desc="Interrupt Disable Register";
        hk="Interrupt Disable Register";
        access="memorymapped"; address=0xFFFCC00C}
    AT91C_US3_MR {desc="Mode Register";
        hk="Mode Register";
        access="memorymapped"; address=0xFFFCC004}
    AT91C_US3_XXR {desc="XON_XOFF Register";
        hk="XON_XOFF Register";
        access="memorymapped"; address=0xFFFCC048}
    AT91C_US3_FIDI {desc="FI_DI_Ratio Register";
        hk="FI_DI_Ratio Register";
        access="memorymapped"; address=0xFFFCC040}
    AT91C_US3_TTGR {desc="Transmitter Time-guard Register";
        hk="Transmitter Time-guard Register";
        access="memorymapped"; address=0xFFFCC028}
    AT91C_US3_BRGR {desc="Baud Rate Generator Register";
        hk="Baud Rate Generator Register";
        access="memorymapped"; address=0xFFFCC020}
    AT91C_US3_RHR {desc="Receiver Holding Register";
        hk="Receiver Holding Register";
        access="memorymapped"; address=0xFFFCC018}
    AT91C_US3_IMR {desc="Interrupt Mask Register";
        hk="Interrupt Mask Register";
        access="memorymapped"; address=0xFFFCC010}
    AT91C_US3_IER {desc="Interrupt Enable Register";
        hk="Interrupt Enable Register";
        access="memorymapped"; address=0xFFFCC008}
# ========== Register definition for PDC_US2 peripheral ========== 
    AT91C_US3_CR {desc="Control Register";
        hk="Control Register";
        access="memorymapped"; address=0xFFFCC000}
    AT91C_US2_PTSR {desc="PDC Transfer Status Register";
        hk="PDC Transfer Status Register";
        access="memorymapped"; address=0xFFFC8124}
    AT91C_US2_TNCR {desc="Transmit Next Counter Register";
        hk="Transmit Next Counter Register";
        access="memorymapped"; address=0xFFFC811C}
    AT91C_US2_RNCR {desc="Receive Next Counter Register";
        hk="Receive Next Counter Register";
        access="memorymapped"; address=0xFFFC8114}
    AT91C_US2_TCR {desc="Transmit Counter Register";
        hk="Transmit Counter Register";
        access="memorymapped"; address=0xFFFC810C}
    AT91C_US2_PTCR {desc="PDC Transfer Control Register";
        hk="PDC Transfer Control Register";
        access="memorymapped"; address=0xFFFC8120}
    AT91C_US2_RCR {desc="Receive Counter Register";
        hk="Receive Counter Register";
        access="memorymapped"; address=0xFFFC8104}
    AT91C_US2_TNPR {desc="Transmit Next Pointer Register";
        hk="Transmit Next Pointer Register";
        access="memorymapped"; address=0xFFFC8118}
    AT91C_US2_RPR {desc="Receive Pointer Register";