at91rm9200.grd

AT91RM9200-BasicTools-IAR4_30A-1_2

        access="memorymapped"; address=0xFFFFF4A8}
# ========== Register definition for DBGU peripheral ========== 
    AT91C_PIOA_OWER {desc="Output Write Enable Register";
        hk="Output Write Enable Register";
        access="memorymapped"; address=0xFFFFF4A0}
    AT91C_DBGU_C2R {desc="Chip ID2 Register";
        hk="Chip ID2 Register";
        access="memorymapped"; address=0xFFFFF244}
    AT91C_DBGU_THR {desc="Transmitter Holding Register";
        hk="Transmitter Holding Register";
        access="memorymapped"; address=0xFFFFF21C}
    AT91C_DBGU_CSR {desc="Channel Status Register";
        hk="Channel Status Register";
        access="memorymapped"; address=0xFFFFF214}
    AT91C_DBGU_IDR {desc="Interrupt Disable Register";
        hk="Interrupt Disable Register";
        access="memorymapped"; address=0xFFFFF20C}
    AT91C_DBGU_MR {desc="Mode Register";
        hk="Mode Register";
        access="memorymapped"; address=0xFFFFF204}
    AT91C_DBGU_FNTR {desc="Force NTRST Register";
        hk="Force NTRST Register";
        access="memorymapped"; address=0xFFFFF248}
    AT91C_DBGU_C1R {desc="Chip ID1 Register";
        hk="Chip ID1 Register";
        access="memorymapped"; address=0xFFFFF240}
    AT91C_DBGU_BRGR {desc="Baud Rate Generator Register";
        hk="Baud Rate Generator Register";
        access="memorymapped"; address=0xFFFFF220}
    AT91C_DBGU_RHR {desc="Receiver Holding Register";
        hk="Receiver Holding Register";
        access="memorymapped"; address=0xFFFFF218}
    AT91C_DBGU_IMR {desc="Interrupt Mask Register";
        hk="Interrupt Mask Register";
        access="memorymapped"; address=0xFFFFF210}
    AT91C_DBGU_IER {desc="Interrupt Enable Register";
        hk="Interrupt Enable Register";
        access="memorymapped"; address=0xFFFFF208}
# ========== Register definition for PDC_DBGU peripheral ========== 
    AT91C_DBGU_CR {desc="Control Register";
        hk="Control Register";
        access="memorymapped"; address=0xFFFFF200}
    AT91C_DBGU_TNCR {desc="Transmit Next Counter Register";
        hk="Transmit Next Counter Register";
        access="memorymapped"; address=0xFFFFF31C}
    AT91C_DBGU_RNCR {desc="Receive Next Counter Register";
        hk="Receive Next Counter Register";
        access="memorymapped"; address=0xFFFFF314}
    AT91C_DBGU_PTCR {desc="PDC Transfer Control Register";
        hk="PDC Transfer Control Register";
        access="memorymapped"; address=0xFFFFF320}
    AT91C_DBGU_PTSR {desc="PDC Transfer Status Register";
        hk="PDC Transfer Status Register";
        access="memorymapped"; address=0xFFFFF324}
    AT91C_DBGU_RCR {desc="Receive Counter Register";
        hk="Receive Counter Register";
        access="memorymapped"; address=0xFFFFF304}
    AT91C_DBGU_TCR {desc="Transmit Counter Register";
        hk="Transmit Counter Register";
        access="memorymapped"; address=0xFFFFF30C}
    AT91C_DBGU_RPR {desc="Receive Pointer Register";
        hk="Receive Pointer Register";
        access="memorymapped"; address=0xFFFFF300}
    AT91C_DBGU_TPR {desc="Transmit Pointer Register";
        hk="Transmit Pointer Register";
        access="memorymapped"; address=0xFFFFF308}
    AT91C_DBGU_RNPR {desc="Receive Next Pointer Register";
        hk="Receive Next Pointer Register";
        access="memorymapped"; address=0xFFFFF310}
# ========== Register definition for AIC peripheral ========== 
    AT91C_DBGU_TNPR {desc="Transmit Next Pointer Register";
        hk="Transmit Next Pointer Register";
        access="memorymapped"; address=0xFFFFF318}
    AT91C_AIC_ICCR {desc="Interrupt Clear Command Register";
        hk="Interrupt Clear Command Register";
        access="memorymapped"; address=0xFFFFF128}
    AT91C_AIC_IECR {desc="Interrupt Enable Command Register";
        hk="Interrupt Enable Command Register";
        access="memorymapped"; address=0xFFFFF120}
    AT91C_AIC_SMR {desc="Source Mode Register";
        hk="Source Mode Register";
        access="memorymapped"; address=0xFFFFF000}
    AT91C_AIC_ISCR {desc="Interrupt Set Command Register";
        hk="Interrupt Set Command Register";
        access="memorymapped"; address=0xFFFFF12C}
    AT91C_AIC_EOICR {desc="End of Interrupt Command Register";
        hk="End of Interrupt Command Register";
        access="memorymapped"; address=0xFFFFF130}
    AT91C_AIC_DCR {desc="Debug Control Register (Protect)";
        hk="Debug Control Register (Protect)";
        access="memorymapped"; address=0xFFFFF138}
    AT91C_AIC_FFER {desc="Fast Forcing Enable Register";
        hk="Fast Forcing Enable Register";
        access="memorymapped"; address=0xFFFFF140}
    AT91C_AIC_SVR {desc="Source Vector Register";
        hk="Source Vector Register";
        access="memorymapped"; address=0xFFFFF080}
    AT91C_AIC_SPU {desc="Spurious Vector Register";
        hk="Spurious Vector Register";
        access="memorymapped"; address=0xFFFFF134}
    AT91C_AIC_FFDR {desc="Fast Forcing Disable Register";
        hk="Fast Forcing Disable Register";
        access="memorymapped"; address=0xFFFFF144}
    AT91C_AIC_FVR {desc="FIQ Vector Register";
        hk="FIQ Vector Register";
        access="memorymapped"; address=0xFFFFF104}
    AT91C_AIC_FFSR {desc="Fast Forcing Status Register";
        hk="Fast Forcing Status Register";
        access="memorymapped"; address=0xFFFFF148}
    AT91C_AIC_IMR {desc="Interrupt Mask Register";
        hk="Interrupt Mask Register";
        access="memorymapped"; address=0xFFFFF110}
    AT91C_AIC_ISR {desc="Interrupt Status Register";
        hk="Interrupt Status Register";
        access="memorymapped"; address=0xFFFFF108}
    AT91C_AIC_IVR {desc="IRQ Vector Register";
        hk="IRQ Vector Register";
        access="memorymapped"; address=0xFFFFF100}
    AT91C_AIC_IDCR {desc="Interrupt Disable Command Register";
        hk="Interrupt Disable Command Register";
        access="memorymapped"; address=0xFFFFF124}
    AT91C_AIC_CISR {desc="Core Interrupt Status Register";
        hk="Core Interrupt Status Register";
        access="memorymapped"; address=0xFFFFF114}
# ========== Register definition for PDC_SPI peripheral ========== 
    AT91C_AIC_IPR {desc="Interrupt Pending Register";
        hk="Interrupt Pending Register";
        access="memorymapped"; address=0xFFFFF10C}
    AT91C_SPI_PTCR {desc="PDC Transfer Control Register";
        hk="PDC Transfer Control Register";
        access="memorymapped"; address=0xFFFE0120}
    AT91C_SPI_TNPR {desc="Transmit Next Pointer Register";
        hk="Transmit Next Pointer Register";
        access="memorymapped"; address=0xFFFE0118}
    AT91C_SPI_RNPR {desc="Receive Next Pointer Register";
        hk="Receive Next Pointer Register";
        access="memorymapped"; address=0xFFFE0110}
    AT91C_SPI_TPR {desc="Transmit Pointer Register";
        hk="Transmit Pointer Register";
        access="memorymapped"; address=0xFFFE0108}
    AT91C_SPI_RPR {desc="Receive Pointer Register";
        hk="Receive Pointer Register";
        access="memorymapped"; address=0xFFFE0100}
    AT91C_SPI_PTSR {desc="PDC Transfer Status Register";
        hk="PDC Transfer Status Register";
        access="memorymapped"; address=0xFFFE0124}
    AT91C_SPI_TNCR {desc="Transmit Next Counter Register";
        hk="Transmit Next Counter Register";
        access="memorymapped"; address=0xFFFE011C}
    AT91C_SPI_RNCR {desc="Receive Next Counter Register";
        hk="Receive Next Counter Register";
        access="memorymapped"; address=0xFFFE0114}
    AT91C_SPI_TCR {desc="Transmit Counter Register";
        hk="Transmit Counter Register";
        access="memorymapped"; address=0xFFFE010C}
# ========== Register definition for SPI peripheral ========== 
    AT91C_SPI_RCR {desc="Receive Counter Register";
        hk="Receive Counter Register";
        access="memorymapped"; address=0xFFFE0104}
    AT91C_SPI_CSR {desc="Chip Select Register";
        hk="Chip Select Register";
        access="memorymapped"; address=0xFFFE0030}
    AT91C_SPI_IDR {desc="Interrupt Disable Register";
        hk="Interrupt Disable Register";
        access="memorymapped"; address=0xFFFE0018}
    AT91C_SPI_SR {desc="Status Register";
        hk="Status Register";
        access="memorymapped"; address=0xFFFE0010}
    AT91C_SPI_RDR {desc="Receive Data Register";
        hk="Receive Data Register";
        access="memorymapped"; address=0xFFFE0008}
    AT91C_SPI_CR {desc="Control Register";
        hk="Control Register";
        access="memorymapped"; address=0xFFFE0000}
    AT91C_SPI_IMR {desc="Interrupt Mask Register";
        hk="Interrupt Mask Register";
        access="memorymapped"; address=0xFFFE001C}
    AT91C_SPI_IER {desc="Interrupt Enable Register";
        hk="Interrupt Enable Register";
        access="memorymapped"; address=0xFFFE0014}
    AT91C_SPI_TDR {desc="Transmit Data Register";
        hk="Transmit Data Register";
        access="memorymapped"; address=0xFFFE000C}
# ========== Register definition for PDC_SSC2 peripheral ========== 
    AT91C_SPI_MR {desc="Mode Register";
        hk="Mode Register";
        access="memorymapped"; address=0xFFFE0004}
    AT91C_SSC2_PTCR {desc="PDC Transfer Control Register";
        hk="PDC Transfer Control Register";
        access="memorymapped"; address=0xFFFD8120}
    AT91C_SSC2_TNPR {desc="Transmit Next Pointer Register";
        hk="Transmit Next Pointer Register";
        access="memorymapped"; address=0xFFFD8118}
    AT91C_SSC2_RNPR {desc="Receive Next Pointer Register";
        hk="Receive Next Pointer Register";
        access="memorymapped"; address=0xFFFD8110}
    AT91C_SSC2_TPR {desc="Transmit Pointer Register";
        hk="Transmit Pointer Register";
        access="memorymapped"; address=0xFFFD8108}
    AT91C_SSC2_RPR {desc="Receive Pointer Register";
        hk="Receive Pointer Register";
        access="memorymapped"; address=0xFFFD8100}
    AT91C_SSC2_PTSR {desc="PDC Transfer Status Register";
        hk="PDC Transfer Status Register";
        access="memorymapped"; address=0xFFFD8124}
    AT91C_SSC2_TNCR {desc="Transmit Next Counter Register";
        hk="Transmit Next Counter Register";
        access="memorymapped"; address=0xFFFD811C}
    AT91C_SSC2_RNCR {desc="Receive Next Counter Register";
        hk="Receive Next Counter Register";
        access="memorymapped"; address=0xFFFD8114}
    AT91C_SSC2_TCR {desc="Transmit Counter Register";
        hk="Transmit Counter Register";
        access="memorymapped"; address=0xFFFD810C}
# ========== Register definition for SSC2 peripheral ========== 
    AT91C_SSC2_RCR {desc="Receive Counter Register";
        hk="Receive Counter Register";
        access="memorymapped"; address=0xFFFD8104}
    AT91C_SSC2_IMR {desc="Interrupt Mask Register";
        hk="Interrupt Mask Register";
        access="memorymapped"; address=0xFFFD804C}
    AT91C_SSC2_IER {desc="Interrupt Enable Register";
        hk="Interrupt Enable Register";
        access="memorymapped"; address=0xFFFD8044}
    AT91C_SSC2_RC1R {desc="Receive Compare 1 Register";
        hk="Receive Compare 1 Register";
        access="memorymapped"; address=0xFFFD803C}
    AT91C_SSC2_TSHR {desc="Transmit Sync Holding Register";
        hk="Transmit Sync Holding Register";
        access="memorymapped"; address=0xFFFD8034}
    AT91C_SSC2_CMR {desc="Clock Mode Register";
        hk="Clock Mode Register";
        access="memorymapped"; address=0xFFFD8004}
    AT91C_SSC2_IDR {desc="Interrupt Disable Register";
        hk="Interrupt Disable Register";
        access="memorymapped"; address=0xFFFD8048}
    AT91C_SSC2_TCMR {desc="Transmit Clock Mode Register";
        hk="Transmit Clock Mode Register";
        access="memorymapped"; address=0xFFFD8018}
    AT91C_SSC2_RCMR {desc="Receive Clock ModeRegister";
        hk="Receive Clock ModeRegister";
        access="memorymapped"; address=0xFFFD8010}
    AT91C_SSC2_CR {desc="Control Register";
        hk="Control Register";
        access="memorymapped"; address=0xFFFD8000}
    AT91C_SSC2_RFMR {desc="Receive Frame Mode Register";
        hk="Receive Frame Mode Register";
        access="memorymapped"; address=0xFFFD8014}
    AT91C_SSC2_TFMR {desc="Transmit Frame Mode Register";
        hk="Transmit Frame Mode Register";
        access="memorymapped"; address=0xFFFD801C}
    AT91C_SSC2_THR {desc="Transmit Holding Register";
        hk="Transmit Holding Register";
        access="memorymapped"; address=0xFFFD8024}
    AT91C_SSC2_SR {desc="Status Register";
        hk="Status Register";
        access="memorymapped"; address=0xFFFD8040}
    AT91C_SSC2_RC0R {desc="Receive Compare 0 Register";
        hk="Receive Compare 0 Register";
        access="memorymapped"; address=0xFFFD8038}
    AT91C_SSC2_RSHR {desc="Receive Sync Holding Register";
        hk="Receive Sync Holding Register";
        access="memorymapped"; address=0xFFFD8030}