📄 cstartup.s79
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;------------------------------------------------------------------------------
;- ATMEL Microcontroller Software Support - ROUSSET -
;------------------------------------------------------------------------------
; The software is delivered "AS IS" without warranty or condition of any
; kind, either express, implied or statutory. This includes without
; limitation any warranty or condition with respect to merchantability or
; fitness for any particular purpose, or against the infringements of
; intellectual property rights of others.
;-----------------------------------------------------------------------------
;- File source : Cstartup.s79
;- Object : Generic CStartup for IAR
;- Compilation flag : None
;-
;- 1.0 14/May/04 JPP : Creation
;------------------------------------------------------------------------------
#include "AT91RM9200_inc.h"
;------------------------------------------------------------------------------
;- Area Definition
;------------------------------------------------------------------------------
;---------------------------------------------------------------
; ?RESET
; Reset Vector.
; Normally, segment INTVEC is linked at address 0.
; For debugging purposes, INTVEC may be placed at other
; addresses.
; A debugger that honors the entry point will start the
; program in a normal way even if INTVEC is not at address 0.
;-------------------------------------------------------------
PROGRAM ?RESET
RSEG INTRAMSTART_REMAP
RSEG INTRAMEND_REMAP
RSEG ICODE:CODE:ROOT(2)
CODE32 ; Always ARM mode after reset
org 0
reset
;------------------------------------------------------------------------------
;- Exception vectors ( before Remap )
;------------------------------------
;- These vectors can be read at address 0 or at RAM address
;- They ABSOLUTELY requires to be in relative addresssing mode in order to
;- guarantee a valid jump. For the moment, all are just looping.
;- If an exception occurs before remap, this would result in an infinite loop.
;- To ensure if a exeption occurs before start application to infinite loop.
;------------------------------------------------------------------------------
B InitReset ; 0x00 Reset handler
undefvec:
B undefvec ; 0x04 Undefined Instruction
swivec:
B swivec ; 0x08 Software Interrupt
pabtvec:
B pabtvec ; 0x0C Prefetch Abort
dabtvec:
B dabtvec ; 0x10 Data Abort
rsvdvec:
B rsvdvec ; 0x14 reserved
irqvec:
B irqvec ; 0x18 IRQ
fiqvec:
B fiqvec ; 0x1c FIQ
;--------------------
;- The reset handler
;--------------------
;------------------------------------------------------------------------------
;- Exception vectors ( after cstartup execution )
;------------------------------------
;- These vectors are read at RAM address after the remap command is performed in
;- the EBI. As they will be relocated at address 0x0 to be effective, a
;- RELATIVE addressing is FORBIDDEN. The only possibility to get an absolute
;- addressing for an ARM vector is to read a PC relative value at a defined
;- offset. It is easy to reserve the locations 0x20 to 0x3C (the 8 next
;- vectors) for storing the absolute exception handler address.
;- The AIC vectoring access vectors are saved in the interrupt and fast
;- interrupt ARM vectors. So, only 5 offsets are required ( reserved vector
;- offset is never used).
;- The provisory handler addresses are defined on infinite loop and can be
;- modified at any time.
;- Note also that the reset is only accessible by a jump from the application
;- to 0. It is an actual software reset.
;- As the 13 (8+5) first location are used by the vectors, the read/write link
;- address must be defined from 0x34 if internal data mapping is required.
;- (use for that the option -rw- base=0x34
;------------------------------------------------------------------------------
PUBLIC VectorTable
PUBLIC eof_VectorTable
VectorTable:
ldr pc, [pc, #0x18] ; 0x00 SoftReset
ldr pc, [pc, #0x18] ; 0x04 UndefHandler
ldr pc, [pc, #0x18] ; 0x08 SWIHandler
ldr pc, [pc, #0x18] ; 0x0C PrefetchAbortHandler
ldr pc, [pc, #0x18] ; 0x10 DataAbortHandler
nop ; 0x14 Reserved
ldr pc, [pc,#-0xF20] ; IRQ : read the AIC
ldr pc, [pc,#-0xF20] ; FIQ : read the AIC
LTORG
;- There are only 5 offsets as the vectoring is used.
DCD SoftReset
DCD UndefHandler
DCD SWIHandler
DCD PrefetchAbortHandler
DCD DataAbortHandler
LTORG
eof_VectorTable:
;- Vectoring Execution function run at absolute addresss
SoftReset
b SoftReset
UndefHandler
b UndefHandler
SWIHandler
b SWIHandler
PrefetchAbortHandler
b PrefetchAbortHandler
DataAbortHandler
b DataAbortHandler
InitReset:
;------------------------------------------------------------------------------
;- Low level Init (APMC, AIC, EBI, ....) by C function AT91F_LowLevelInit
;------------------------------------------------------------------------------
EXTERN AT91F_LowLevelInit
#define __iramstart SFB(INTRAMSTART_REMAP)
#define __iramend SFB(INTRAMEND_REMAP)
;- minumum C initialization
;- call AT91_REG * AT91F_LowLevelInit( unsigned int * Vector,unsigned int * InternalRam)
; r0 = AT91F_LowLevelInit(&VectorTable,&InternalRAM)
ldr r13,=__iramend ; temporary stack in internal RAM
ldr r1,=__iramstart ; Get internal RAM address
add_pc: sub r0,pc,#((add_pc+8)-VectorTable)
;--Call Low level init function in ABSOLUTE through the Interworking
ldr r2,=AT91F_LowLevelInit
mov lr, pc
bx r2
;--------------------------------------------
;- Remap Command and jump on ABSOLUT address
;--------------------------------------------
;------------------------------------------------------------------------------
;- The Reset Handler after Remap
;-------------------------------
;- From here, the code is executed from its link address, ie. 0x100 0000.
;------------------------------------------------------------------------------
InitRemap:
;------------------------------------------------------------------------------
;- Stack Sizes Definition
;------------------------
;- Interrupt Stack requires 2 words x 8 priority level x 4 bytes when using
;- the vectoring. This assume that the IRQ_ENTRY/IRQ_EXIT macro are used.
;- The Interrupt Stack must be adjusted depending on the interrupt handlers.
;- Fast Interrupt not requires stack If in your application it required you must
;- be definehere.
;- Other stacks are defined by default to save one word each.
;- The System stack size is not defined and is limited by the free internal
;- SRAM.
;- User stack size is not defined and is limited by the free external SRAM.
;------------------------------------------------------------------------------
IRQ_STACK_SIZE EQU (2*8*4) ; 2 words per interrupt priority level
FIQ_STACK_SIZE EQU (0*4) ; 0 words
ABT_STACK_SIZE EQU (1*4) ; 1 word
UND_STACK_SIZE EQU (1*4) ; 1 word
;------------------------------------------------------------------------------
;- Top of Stack Definition
;-------------------------
;- Fast Interrupt, Interrupt, Abort, Undefined and Supervisor Stack are located
;- at the top of internal memory in order to speed the exception handling
;- context saving and restoring.
;- User (Application, C) Stack is located at the top of the external memory.
;------------------------------------------------------------------------------
#define TOP_EXCEPTION_STACK (AT91C_SRAM_AFTER_REMAP+AT91C_SRAM_AFTER_REMAP_SIZE)
ARM_MODE_USER EQU 0x10
ARM_MODE_FIQ EQU 0x11
ARM_MODE_IRQ EQU 0x12
ARM_MODE_SVC EQU 0x13
ARM_MODE_ABORT EQU 0x17
ARM_MODE_UNDEF EQU 0x1B
ARM_MODE_SYS EQU 0x1F
I_BIT EQU 0x80
F_BIT EQU 0x40
T_BIT EQU 0x20
;------------------------------------------------------------------------------
;- Setup the stack for each mode
;-------------------------------
mov r0, r13
;- Set up Fast Interrupt Mode and set FIQ Mode Stack
msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
mov r13, r0 ; Init stack FIQ
sub r0, r0, #FIQ_STACK_SIZE
;- Set up Interrupt Mode and set IRQ Mode Stack
msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
mov r13, r0 ; Init stack IRQ
sub r0, r0, #IRQ_STACK_SIZE
;- Set up Abort Mode and set Abort Mode Stack
msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT
mov r13, r0 ; Init stack Abort
sub r0, r0, #ABT_STACK_SIZE
;- Set up Undefined Instruction Mode and set Undef Mode Stack
msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT
mov r13, r0 ; Init stack Undef
sub r0, r0, #UND_STACK_SIZE
;- Set up Supervisor Mode and set Supervisor Mode Stack
msr CPSR_c, #ARM_MODE_SVC | I_BIT
mov r13, r0 ; Init stack Undef
;----------------------------------------
; Read/modify/write CP15 control register
;----------------------------------------
MRC p15, 0, r0, c1, c0,0 ; read cp15 control registre (cp15 r1) in r0
ldr r3, =0xC0000080 ; Reset bit :Little Endian end fast bus mode
ldr r4, =0xC0000000 ; Set bit :Asynchronous clock mode, Not Fast Bus
BIC r0, r0, r3
ORR r0, r0, r4
MCR p15, 0, r0, c1, c0,0 ; write r0 in cp15 control registre (cp15 r1)
;------------------------------------------------------------------------------
;- Before Init C Initialise C variables you can copy the from FLASH to RAM
;------------------------------------------------------------------------------
;- Enable interrupt
msr CPSR_c, #ARM_MODE_SVC
;------------------------------------------------------------------------------
;- Branch on C code Main function (with interworking)
;----------------------------------------------------
;---------------------------------------------------------------
; ?CSTARTUP
;---------------------------------------------------------------
EXTERN __segment_init
EXTERN main
; Initialize segments.
; __segment_init is assumed to use
; instruction set and to be reachable by BL from the ICODE segment
; (it is safest to link them in segment ICODE).
ldr r0,=__segment_init
mov lr, pc
bx r0
PUBLIC __main
?jump_to_main:
ldr lr,=?call_exit
ldr r0,=main
__main:
bx r0
?call_exit:
;------------------------------------------------------------------------------
;- Loop for ever
;---------------
;- End of application. Normally, never occur.
;- Could jump on Software Reset ( B 0x0 ).
;------------------------------------------------------------------------------
End
b End
;------------------------------------------------------------------------------
;- Manage exception
;---------------
;- This module The exception must be ensure in ARM mode
;------------------------------------------------------------------------------
;---------------------------------------------------------------
; ?EXEPTION_VECTOR
; This module is only linked if needed for closing files.
;---------------------------------------------------------------
; MODULE ?EXEPTION_VECTOR
PUBLIC AT91F_Default_FIQ_handler
PUBLIC AT91F_Default_IRQ_handler
PUBLIC AT91F_Spurious_handler
CODE32 ; Always ARM mode after exeption
AT91F_Default_FIQ_handler
b AT91F_Default_FIQ_handler
AT91F_Default_IRQ_handler
b AT91F_Default_IRQ_handler
AT91F_Spurious_handler
b AT91F_Spurious_handler
ENDMOD
;---------------------------------------------------------------
; ?INITTAB
; This module is only linked if needed by e.g. __segment_init.
; The INITTAB segment contains segment initialization entries.
; See segment_init.h.
;---------------------------------------------------------------
MODULE ?INITTAB
RSEG INITTAB:CONST(2) ; Declaration for SFB/SFE below
RSEG HUGE_C:CONST:NOROOT(2)
DATA
PUBLIC __segment_begin_INITTAB
PUBLIC __segment_end_INITTAB
__segment_begin_INITTAB DC32 SFB(INITTAB)
__segment_end_INITTAB DC32 SFE(INITTAB)
ENDMOD
END
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